ST7DALI datasheet(77/141 Pages) STMICROELECTRONICS

77 / 141 page

ST7DALI

77/141

DALI COMMUNICATION MODULE (cont’d)

DCM CONTROL REGISTER (DCMCR)

Read / Write

Reset Value: 0000 0000 (00h)

Bits 7:4 = Reserved. Forced by hardware to 0.

Bit 3 = DCME DALI Communication Enable.

This bit is set/cleared by software and cleared by

hardware after a reset.

When set, it enables DALI communication. It also

resets the entire internal finite state machine.

0: The DCM is not enable to receive/transmit

1: The DCM is enable to receive/transmit

Bit 2 = RTA Receive/Transmit Acknowledge.

This bit is reset by hardware after it has been set

by software. It is cleared after a reset.

This bit must be set, after a first DALI frame recep-

tion or transmission, to allow the DCM to perform

the next DALI communication.

0: No acknowledge

1: Acknowledge

Bit 1 = RTS Receive/Transmit state.

This bit is set/cleared by software and cleared by

hardware after a reset.

This bit must be set to ’1’ after a forward frame is

received, if a backward frame is required. This bit

must be cleared after a backward frame is trans-

mitted, if a forward frame is required.

0: The DCM is set to Receive state

1: The DCM is set to Transmit state

Bit 0 = FTS Force Transmit state.

This bit is set/cleared by software and cleared by

hardware after a reset.

When this bit is set, the DCM is forced into Trans-

mit state. Preferably before forcing the DCM into

Transmit state, the user should reset and set the

DCME bit in the DCMCR register. An interrupt flag

(ITF) is generated after a forced transmission.

0: The DCM is not forced to Transmit state

1: The DCM is forced to Transmit state

DCM CONTROL/STATUS REGISTER

(DCMCSR)

Read only (except for bit 7)

Reset Value: 0000 0000 (00h)

Bit 7 = ITE Interrupt Enable.

This bit is set/cleared by software and cleared by

hardware after a reset.

When set, this bit allows the generation of DALI in-

terrupts.

0: DCM interrupt (ITF) disabled

1: DCM interrupt (ITF) enabled

Bit 6 = ITF Interrupt Flag. (Read only)

This bit is set/cleared by hardware and read by

software.

This bit is set after the end of the "backward frame"

transmission or the "forward frame" reception. It is

cleared by setting the RTA bit in the DCMCR reg-

ister. It is set after a forced transmission (see the

FTS bit).

0: Not the end of reception/transmission

1: End of reception/transmission

Bit 5 = EF Error Flag. (Read only)

This bit is set/cleared by hardware. It is cleared by

reading the DCMCSR register.

This bit is set when either the DALI data format re-

ceived is wrong or an interface failure is detected.

0: No data format error during reception

1: Data format error during reception

Bit 4 = RTF Receive/Transmit Flag. (Read only)

This bit is set/reset by hardware and read by soft-

ware.

0: The DCM is in Transmit state

1: The DCM is in Receive state

Bits 3:0 = DCMCSR[3:0] Clock counter value.

(Read only) These bits are set/cleared by hard-

ware and read by software.

The value of the 4-bit sample clock counter (inte-

ger range 0 to 15). The clock counter value is load-

ed in the DCMCSR register when a DALI change

of phase signal is detected (edge trigger). Refer to

Figure 44.

DCME

RTA

RTS

FTS

ITE

ITF

RTF

CK3

CK2

CK1

CK0

ST7DALI 数据表(PDF) 77 Page - STMicroelectronics

ST7DALI 数据表(HTML) 77 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

ST7DALI 数据表(PDF) 77 Page - STMicroelectronics

ST7DALI 数据表(HTML) 77 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载