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ST7DALI 数据表(PDF) 11 Page - STMicroelectronics |
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ST7DALI 数据表(HTML) 11 Page - STMicroelectronics |
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11 / 141 page  ST7DALI 11/141 Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value. 3. For a description of the Debug Module registers, see ICC reference manual. 0037h ITC EICR External Interrupt Control Register 00h R/W 0038h MCC MCCSR Main Clock Control/Status Register 00h R/W 0039h 003Ah Clock and Reset RCCR SICSR RC oscillator Control Register System Integrity Control/Status Register FFh 0000 0XX0h R/W R/W 003Bh Reserved area (1 byte) 003Ch ITC EISR External Interrupt Selection Register 0Ch R/W 003Dh to 003Fh Reserved area (3 bytes) 0040h 0041h 0042h 0043h 0044h 0045h DALI DCMCLK DCMFA DCMFD DCMBD DCMCR DCMCSR DALI Clock Register DALI Forward Address Register DALI Forward Data Register DALI Backward Data Register DALI Control Register DALI Control/Status Register 00h 00h 00h 00h 00h 00h R/W R/W R/W R/W R/W R/W 0046h to 0048h Reserved area (3 bytes) 0049h 004Ah AWU AWUPR AWUCSR AWU Prescaler Register AWU Control/Status Register FFh 00h R/W R/W 004Bh 004Ch 004Dh 004Eh 004Fh 0050h DM3) DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L DM Control Register DM Status Register DM Breakpoint Register 1 High DM Breakpoint Register 1 Low DM Breakpoint Register 2 High DM Breakpoint Register 2 Low 00h 00h 00h 00h 00h 00h R/W R/W R/W R/W R/W R/W 0051h to 007Fh Reserved area (47 bytes) Address Block Register Label Register Name Reset Status Remarks 1 |
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