DocID031029 Rev 3

13/37

ST8500

Device architecture

37

2.2.15

Pseudo random number generator (PRNG)

The ST8500 embeds a PRNG processor that provides a pseudo random 32-bit value. Initial

seed can be configured by software.

2.2.16

CRC (cyclic redundancy check) calculation unit

The cyclic redundancy check (CRC) is a widely used method for detecting errors. The CRC

calculation unit is used to get a CRC code in a flexible way using a configurable polynomial.

The output data size can be selected between 8, 16, 24 or 32 bits.

The input data size can be configured between 1, 8, 16, 24 or 32 bits with selectable bit and

byte endianness.

The CRC unit allows the specification of the initial value (all zero, all one, or a generic value)

and the possibility to select an automatic XOR with all one when reading the data output.

2.3

Inter-processor communication (IPC)

The Cortex™-M4 core and the real-time engine (RTE) communicate by means of an

additional 8-kByte shared static RAM. This memory can be accessed by the two cores

through an interprocessor communication block that guarantees coherent and consistent

read and modify operations, to provide several functionalities to the system, among the

others:



Configuration of real-time engine modes and functionalities during the normal working

operations



Data and information exchange between the Cortex™-M4 and real-time engine in both

directions.

2.4

Cortex™ memories

2.4.1

Embedded SRAM (instruction and data)

The ST8500 device embeds 256 kByte of the SRAM for a fast code execution. This SRAM

can be used also to store data with penalties in the concurrent instruction and data access.

The data SRAM start address is 0x00050000, the end address is 0x0008FFFF.

2.4.2

Embedded SRAM (data only)

The ST8500 device embeds 96 kBytes of the SRAM for data management. The

Cortex™-M4 can perform byte, half word (16 bits) or full word (32 bits) access to the SRAM

at maximum speed, with zero wait states for both read and write operations. The data

SRAM start address is 0x00090000, the end address is 0x000A7FFF.

2.4.3

Embedded ROM

The ST8500 device embeds a ROM memory used to store the bootloader program written

during the device production phase.