DocID031029 Rev 3

19/37

ST8500

Device architecture

37

Figure 5. ST8500 system power modes transition diagram

Clock gating is available in any modes for peripherals and clock sources in order to save all

the dynamic power contributions related to the resources not used by the application.

2.7

Boot modes and system programmability

ST8500 boot mode is defined by the status of the three pins GPIO3_0/BOOT0,

GPIO3_1/BOOT1, GPIO3_2/BOOT2 when the device awakes from a reset condition (either

power-on, hardware or software reset), the correspondence between the value of BOOTx

pins and the boot mode is shown in Table 6.

The application and RTE codes can be either downloaded by the external host (through SPI

or UART interface) or written as binary images on one external SPI Flash (either up to

4 Mbit for the small configuration or from 8 Mbit for the large configuration). The internal

bootloader takes the responsibility to load the codes in the proper cores and to start running

them. If “Reserved2” mode is selected an endless loop is performed. If one of the

Table 6. Boot modes selection

Boot pins

Boot mode

BOOT2

BOOT1

BOOT0

0

0

0

Boot from UART host interface

0

0

1

Boot from SPI host interface

0

1

0

Boot from SPI external Flash (large configuration)

0

1

1

Boot from SPI external Flash (small configuration)

100

Reserved1

101

Reserved1

110

Reserved1

111

Reserved2