ST8500TR datasheet(8/37 Pages) STMICROELECTRONICS

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Device architecture

ST8500

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DocID031029 Rev 3

2.2

Protocol core subsystem

2.2.1

ARM® Cortex™-M4F core

The Cortex™-M4F processor is built on a high-performance processor core, with a 3-stage

pipeline Harvard architecture, making it ideal for demanding embedded applications. The

processor delivers exceptional power efficiency through an efficient instruction set and

extensively optimized design, providing high end processing the hardware including

IEEE754-compliant single precision (32-bit) floating point computation, a range of a single

cycle and SIMD multiplication and multiply with accumulate capabilities, saturating

arithmetic and dedicated hardware division.

To facilitate the design of cost-sensitive devices, the Cortex™-M4F processor implements

tightly coupled system components that reduce the processor area while significantly

improving interrupt handling and system debug capabilities. The Cortex™-M4F processor

implements a version of the Thumb® instruction set based on the Thumb®-2 technology,

ensuring high code density and reduced program memory requirements. The Cortex™-M4F

instruction set provides the exceptional performance expected by a modern 32-bit

architecture, with the high code density of 8-bit and 16-bit microcontrollers.

The Cortex™-M4F processor provides multiple interfaces using the AMBA™ technology to

provide high-speed, low latency memory accesses. It supports unaligned data accesses

and implements atomic bit manipulation that enables faster peripheral controls, system

spinlocks and thread-safe Boolean data handling.

2.2.2

Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (Cortex™-M4F and RTE) and

the slaves (RAM, AHB and APB peripherals and real-time engine) and ensures a seamless

and efficient operation even when several high-speed peripherals work simultaneously.

Table 2. Cortex™-M4F core configuration

Component

Presence

Comment

MPU_PRESENT

Memory protection unit (MPU) is not present

NUM_IRQ

N/A

Number of interrupts: 32

LVL_WIDTH

N/A

Interrupt priority width: 3

DEBUG_LVL

N/A

Minimum debug. 2 breakpoints, 1 watchpoint, no Flash patch

JTAG

Yes

JTAG-DP is included. The SW-DP is always included.

ITM

Yes

Instrumentation Trace Macrocell

™

DWT

Yes

Data watchpoint and trace

WIC

Wake-up interrupt controller (WIC) is not present

Bit banding region is not present

FPU

Yes

Floating point unit present (single precision)

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