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ST8500TR 数据表(PDF) 31 Page - STMicroelectronics |
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ST8500TR 数据表(HTML) 31 Page - STMicroelectronics |
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31 / 37 page ![]() DocID031029 Rev 3 31/37 ST8500 Electrical characteristics 37 5.4.2 Reception path characteristics Table 19. Receiver input referred noise Symbol Parameter(1) Conditions Min. Typ. Max. Unit V(RX_INP - RX_INN) Receiver input referred noise CENELEC-A (35 kHz to 95 kHz) - 17 - dBµV CENELEC -B (95 kHz to 125 kHz) - 14 - dBµV CENELEC -C (125 kHz to 140 kHz) - 11 - dBµV CENELEC -D (140 kHz to 148 kHz) - 8 - dBµV ARIB STD-T84 (35 kHz to 400 kHz) - 24 - dBµV FCC-LOW (35 kHz to 125 kHz) - 19 - dBµV G3-FCC (150 kHz to 490 kHz) - 24 - dBµV 1. Guaranteed by design, not tested in production. Table 20. PGA characteristics Symbol Parameter Conditions Min. Typ. Max. Unit V(RX_INP), V(RX_INN) Receiver input maximum voltage Single-ended mode - 7.5 - V p-p V(RX_INP -RX_INN) Receiver input maximum voltage Differential mode - 15 - V p-p V(RX_INP), V(RX_INN) Receiver input bias voltage - - (AVDD_2V5 AFE) * 0.475 -V Z(RX_INP), Z(RX_INN) Receiver input impedance Single-ended - 5 - k GPGA PLC PGA minimum gain - - -18 - dB PLC PGA maximum gain - - 54 - dB GPGA Step PLC PGA gain step - - 3 - dB Table 21. ADC characteristics Symbol Parameter Conditions Min. Typ. Max. Unit ADC input range - Differential mode - 1.8 - V p-p Resolution - - - 11 - bit |
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