Device architecture

ST8500

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DocID031029 Rev 3

2.2.11

Serial peripheral interface (SPI)

Three SPI interfaces (SPI0 to SPI2) allow communication up to 50 Mbit/s in master and up

to 24 Mbit/s slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit pre-

scaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16

bits. The SPI interfaces support NSS pulse mode, TI mode and hardware CRC calculation.

2.2.12

protocol, arbitration and timing. In addition to receiving and transmitting data, this interface

converts it from the serial to the parallel format and vice versa. The interrupts are enabled or

a clock pin (SCL).

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Slave and master modes, multimaster capability

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Standard-mode (Sm), with a bitrate up to 100 kbit/s

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Fast-mode (Fm), with a bitrate up to 400 kbit/s

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7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

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Programmable setup and hold times

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Optional clock stretching

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System management bus (SMBus) specification rev 2.0 compatibility:

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Hardware PEC (packet error checking) generation and verification with ACK

control

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Address resolution protocol (ARP) support

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SMBus alert

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Power System Management Protocol (PMBus™) specification rev 1.1 compatibility

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communication speed to be independent from the PCLK clock reprogramming.

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Programmable analog and digital noise filters

2.2.13

AES engine

The ST8500 embeds a hardware AES peripheral that implements an advanced standard

cryptographic algorithm according to the NIST FIPS 197. The block processes 128-bit data

blocks using a key with the following possible sizes: 128, 192, 256 bits. The peripheral also

supports the following modes: “Electronic Code Book” (ECB), “Cipher Block Chaining”

(CBC), “Counter mode” (CTR), “Galois/Counter Mode” (GCM), GMAC and CCM modes.

The peripheral is able to encrypt and decrypt data. Interrupt can be generated when one

operation is finished.

2.2.14

True random number generator (TRNG)

The ST8500 embeds a TRNG processor based on a continuous analog noise that provides

a random 16-bit value. To avoid pseudo random sequences, two consecutive accesses

have to be performed when the ready bit in the status register is set to 1.