ADAV801ASTZ datasheet(39/56 Pages) AD

39 / 56 page

ADAV801

Rev. 0 | Page 39 of 56

RxValid

Emphasis

Mask

nAudio

Mask

onA

Preamble

Mask

CRCError

Mask

Stream

Mask

BiPhas

Parity

Mask

Lock Mask

Table 40. Receiver Error Mask Register

Mask

ity

udio

ADDRESS = 0011001 (0x19)

RxValidity Mask

rating an interrupt.

Masks the RxValidity bit from gene

0 = RxValidity bit does not generate an interrupt.

terrupt.

an interrupt.

0 = NonAudio bit does not generate an interrupt.

1 = NonAudio bit generates an interrupt.

nAudio preamble bit from generating an interrupt.

0 = NonAudio preamble bit does not gene

e an interru

onAudio preamble bit generates an interrupt.

ask

NoStream Mask

BiPhase/Parity Mask

an interrupt.

1 = RxValidity bit generates an interrupt.

Emphasis Mask

Masks the emphasis bit from generating an in

0 = Emphasis bit does not generate an interrupt.

1 = Emphasis bit generates an interrupt.

NonAudio Mas

Masks the NonAudio bit from generating

NonAudio Preamble

Masks the No

Mask

rat

pt.

1 = N

CRCError M

Masks the CRCError bit from generating an interrupt.

0 = CRCError bit does not generate an interrupt.

1 = CRCError bit generates an interrupt.

Masks the NoStream bit from generating an interrupt.

0 = NoStream bit does not generate an interrupt.

1 = NoStream bit generates an interrupt.

Masks the BiPhase/Parity bit from generating

0 = BiPhase/Parity bit does not generate an interrupt.

1 = BiPhase/Parity bit generates an interrupt.

Lock Mask

Masks the Lock bit from generating an interrupt.

0 = Lock bit does not generate an interrupt.

1 = Lock bit generates an interrupt.

Table 41. Sample Rate Co

RES

TOO_SLOW

OVRL

OVRR

MUTE_IND

nverter Error Register (Read Only)

ADDRESS = 0011010 (0x1A)

TOO_SLOW

This bit is set, when the clock to the SRC is too slow, that is, there are not enough clock cycles to complete the

internal convolution.

OVRL

This bit is set, when the left output data of the sample rate converter has gone over the full-scale range and has been

clipped. This bit is not cleared until the register is read.

OVRR

This bit is set, when the right output data of the sample rate converter has gone over the full-scale range and has

been clipped. This bit is not cleared until the register is read.

MUTE_IND

Mute indicated. This bit is set, when the SRC is in fast mode and clicks or pops can be heard in the SRC output data.

The output of the SRC can be muted, if required, until the SRC is in slow mode. Once read, this bit remains in its state

and does not generate an interrupt until it has changed state.

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