ADAV801ASTZ datasheet(21/56 Pages) AD

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ADAV801

Rev. 0 | Page 21 of 56

ut samples added to the write pointer of the

(512 − 16)/64 taps = 7.75

for short group delay and

(512 − 64)/64 taps = 7

for long group delay.

o of fS_IN/fS_OUT

The number of inp

FIFO on the SRC is 16 plus Bit 6 to Bit 0 of the group delay

prevent the read pointer to the FIFO from running ahead of the

write pointer. When set, Bit 7 of the group delay and mute-in

write address pointer is useful for applications in which small

changes in the sample rate ratio between fS_IN and fS_OUT are

expected. The maximum decimation rate can be calculated

from the RAM word depth and the group delay as

The digital servo loop is essentially a ramp filter that provides

the initial pointer to the address in RAM and ROM for the start

of the FIR convolution. The RAM pointer is the integer output

of the ramp filter, and the ROM is the fractional part. The

digital servo loop must provide excellent rejection of jitter on

the fS_IN and fS_OUT clocks, as well as measure the arrival of the

fS_OUT clock within 4.97 ps. The digital servo loop also divides

the fractional part of the ramp output by the rati

to dynamically alter the ROM coefficients when fS_IN > fS_OUT.

REG 0x00

BITS 1–0

REG 0x76

BIT 0

REG 0x76

BIT 1

REG 0x62

BITS 7–6

DIR

PLAYBACK

AUXILIARY IN

ADC

SRC

MCLK

SRC

OUTPUT

SRC

INPUT

Figure 33. Clock and Datapath Control on the SCR

The digital servo loop is implemented with a multirate filter. To

ttle the digital servo loop filter more quickly upon startup or a

added to the

ample rate is

easonable value, the digital

During fast mode, the MUTE_OUT bi

e error

he u

at clicks

ght

pres

l audio

tput of

e mu

Bit 7 of he group delay and

l t

ged to

he MU

an be

n inter

when the SRC

ing sample rate

onve

ly.

/fS_IN) × 220 ratio for

change in the sample rate, a fast mode has been

filter. When the digital servo loop starts up or the s

changed, the digital servo loop enters fast mode to adjust and

settle on the new sample rate. Upon sensing that the digital

servo loop is settling down to a r

servo loop returns to normal (or slow) mode.

t in the sample rat

regist r is asserted to let t

ser know th

or pops mi

ent in the digita

data. The ou

the SRC can

ted by asserting

mute registe

unti he SRC has chan

slow mode. T

TE_OUT bit

set to generate a

rupt

changes to

slow

ode, indicating that t e data is be

rted accurate

The frequency responses of the digital servo loop for fast mod

and slow mode are shown in Figure 34. The FIR filter is a 64-tap

filter when fS_OUT ≥ fS_IN and is (fS_IN/fS_OUT) × 64 taps when fS_IN >

fS_OUT. The FIR filter performs its convolution by loading in the

starting address of the RAM address pointer and the ROM

address pointer from the digital servo loop at the start of the

fS_OUT period. The FIR filter then steps through the RAM by

decrementing its address by 1 for each tap, and the ROM

pointer increments its address by the (fS_OUT

fS_IN > fS_OUT or 220 for fS_OUT ≥ fS_IN. Once the ROM address rolls

over, the convolution is completed.

FREQUENCY (Hz)

–20

–40

–60

–80

–100

–120

–140

–160

–180

–200

0.01

0.1

100

10k

100k

SLOW MODE

FAST MODE

–220

Figure 34. Frequency Response of the Digital Servo Loop. fS_IN is the X-Axis,

fS_OUT = 192 KHz, Master Clock is 30 MHz

The convolution is performed for both the left and right

channels, and the multiply accumulate circuit used for the

convolution is shared between the channels. The fS_IN/fS_OUT

sample rate ratio circuit is used to dynam cally alter the

in the ROM when fS_IN > fS_OUT. The ratio is

calculated by comparing the output of an fS_OUT counter to the

output of an fS_IN counter. If fS_OUT > fS_IN, the ratio is held at one.

, the sample rate ratio is updated, if it is different

by more than two fS_OUT periods from the previous fS_OUT to fS_IN

comparison. This is done to provide some hysteresis to prevent

coefficients

If fS_IN > fS_O

the filter length from oscillating and causing distortion.

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