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LSM303C 数据表(PDF) 24 Page - STMicroelectronics

部件名 LSM303C
功能描述  Ultra-compact high-performance eCompass module: 3D accelerometer and 3D magnetometer
PDF  53 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

LSM303C 数据表(HTML) 24 Page - STMicroelectronics

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Digital interfaces
LSM303C
24/53
DocID024975 Rev 2
6
Digital interfaces
The registers embedded inside the LSM303C may be accessed through both the I2C and
SPI serial interfaces. The latter may be SW-configured to operate in 3-wire interface mode.
The serial interfaces are mapped onto the same pads. To select/exploit the I2C interface, the
CS line must be tied high (i.e. connected to Vdd_IO).
6.1
I2C serial interface
The LSM303C I2C is a bus slave. The I2C is employed to write data into registers whose
content can also be read back.
The relevant I2C terminology is given in the table below.
There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial
data line (SDA). The latter is a bidirectional line used for sending and receiving the data
to/from the interface. Both the lines must be connected to Vdd_IO through an external pull-
up resistor. When the bus is free, both the lines are high.
The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as with the
normal mode.
In order to disable the I2C block for the accelerometer, CTRL_REG4_A (I2C_DISABLE)
must be written to ‘1’, while for magnetometer CTRL_REG3_M (I2C_DISABLE) must be
written to ‘1’.
Table 10. Serial interface pin description
Pin name
Pin description
CS_XL, CS_MAG
SPI enable
I2C/SPI mode selection (1: SPI idle mode / I2C communication
enabled; 0: SPI communication mode / I2C disabled)
SCL
SPC
I2C serial clock (SCL)
SPI serial port clock (SPC)
SDA
SDI
SDO
I2C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
Table 11. Serial interface pin description
Term
Description
Transmitter
The device which sends data to the bus
Receiver
The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals and terminates a
transfer
Slave
The device addressed by the master
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