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LIS25BA 数据表(PDF) 19 Page - STMicroelectronics |
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LIS25BA 数据表(HTML) 19 Page - STMicroelectronics |
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19 / 32 page ![]() DocID031510 Rev 4 19/32 LIS25BA TDM interface specifications 32 4.5.3 Configuration 3 Delayed: SLOT0 data MSB is sampled on the second rising edge of BCLK after rising edge of WCLK (delayed I²C register TDM_CTRL_REG (2Eh) bit 6 equal to one) Data valid: data valid on the rising edge of BCLK (data_valid I²C register TDM_CTRL_REG (2Eh) bit 5 equal to zero) Figure 11. WCLK, SDOUT change on the falling edge of BCLK and are valid on the rising edge of BCLK, delayed Note: Setup and hold times are defined in Table 6: TDM interface characteristics. 4.5.4 Configuration 4 Delayed: SLOT0 data MSB is sampled on the second falling edge of BCLK after rising edge of WCLK (delayed I²C register TDM_CTRL_REG (2Eh) bit 6 equal to one) Data valid: data valid on the falling edge of BCLK (data_valid I²C register TDM_CTRL_REG (2Eh) bit 5 equal to one) Figure 12. WCLK, SDOUT change on the rising edge of BCLK and are valid on the falling edge of BCLK, delayed Note: Setup and hold times are defined in Table 6: TDM interface characteristics. |
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