I²C- inter-IC control interface

LIS25BA

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acknowledge after each byte of data has been received. The I²C embedded inside the

LIS25BA behaves like a slave device and the following protocol must be adhered to. After

the start condition (ST) a slave address is sent, once a slave acknowledge has been

returned (SAK), an 8-bit sub-address will be transmitted (SUB): the 7 LSB represent the

actual register address while the MSB enables address auto-increment. If the MSB of the

SUB field is ‘1’, the SUB (register address) will be automatically incremented to allow

multiple data read/write at increasing addresses. Otherwise if the MSB of the SUB field is

‘0’, the SUB will remain unchanged and multiple read/write on the same address can be

performed. If the LSB of the slave address is ‘1’ (read), a repeated START (SR) condition

will have to be issued after the sub-address byte; if the LSB is ‘0’ (write) the master will

transmit to the slave with direction unchanged.

5.3

I²C slave address

The slave address is equal to 001100yx (TDM mode, where y = not(I2C_A0 pin)) or in case

of writing or reading respectively.

5.4

I²C read and write sequences

Previous subsequences are used for the actual write and read sequences described in the

tables below.

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number

of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant Bit

(MSB) first. If a receiver can’t receive another complete byte of data until it has performed

some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait

state. Data transfer only continues when the receiver is ready for another byte and releases

the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to

receive because it is performing some real time function) the data line must be left HIGH by

the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line

while the SCL line is HIGH is defined as a STOP condition (SP). Each data transfer must be

terminated by the generation of a STOP condition.

Table 12. Transfer when master is writing one byte to slave

Master

ST

SAD + W

SUB

DATA

SP

Slave

SAK

SAK

SAK

Table 13. Transfer when master is writing multiple bytes to slave

Master

ST

SAD + W

SUB

DATA

DATA

SP

Slave

SAK

SAK

SAK

SAK

Table 14. Transfer when master is receiving (reading) one byte of data from slave

Master

ST

SAD + W

SUB

SR

SAD + R

NMAK

SP

Slave

SAK

SAK

SAK

DATA

Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave

Master ST SAD+W

SUB

SR SAD+R

MAK

MAK

NMAK SP

Slave

SAK

SAK

SAK

DATA

DATA

DATA