DocID031510 Rev 4

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LIS25BA

Register description

32

8.5

TDM_CTRL_REG (2Eh)

Table 23. TDM_CTRL_REG register

8.6

AXES_CTRL_REG (2Fh)

Table 25. AXES_CTRL_REG register

TDM_pd

Delayed

data_valid

mapping

1. For proper operation of the device, this bit must be set to ‘0’.

WCLK_fq1

WCLK_fq0

0(1)

Table 24. TDM_CTRL_REG register description

TDM_pd

TDM enable. Default value: 1

(0: TDM on; 1: TDM off)

Delayed

TDM delayed configuration. Default value: 1

(0: TDM no delayed configuration; 1: TDM delayed configuration)

data_valid

TDM data valid. Default value: 1

(0: data valid on the rise edge of BCLK; 1: data valid on the falling edge of BCLK)

mapping

TDM mapping. Default value: 1

(0: AXEX --> SLOT0; AXEY --> SLOT1; AXEZ --> SLOT2;

1: AXEX --> SLOT4; AXEY --> SLOT5; AXEZ --> SLOT6)

WCLK_fq [1:0]

TDM clock frequencies. Default value: 00

(00: WCLK = 8 kHz;

01: WCLK = 16 kHz;

10: WCLK = 24 kHz)

AXISZ_EN AXISY_EN AXISX_EN

1. For proper operation of the device, this bit must be set to ‘0’.

0(1)

0(1)

0(1)

ODR_AUTO_EN

Table 26. AXES_CTRL_REG register description

AXISZ_EN

Z-axis enable. Default value: 1

(0: disabled; 1: enabled)

AXISY_EN

Y-axis enable. Default value: 1

(0: disabled; 1: enabled)

AXISX_EN

X-axis enable. Default value: 1

(0: disabled; 1: enabled)

ODR_AUTO_EN ODR AUTO enable. Default value: 1

1. In this case it is mandatory to set TDM_CTRL_REG (2Eh) bits 2 and 1 to match the WCLK sampling rate

and TDM_cmax (24h-25h) to match the BCLK/WCLK ratio

2. LIS25BA automatically measures the ratio r = MCLK/WCLK. The WCLK frequency is internally

determined as FW=12.288 MHz/r. FW will be used to configure automatically the decimation ratio between

the ADC and TDM input data rate (same as TDM output data rate) bypassing TDM_CTRL_REG (2Eh) bits

2 and 1 configuration. When ODR_AUTO is ‘1’ also the BCLK/WCLK ratio is automatically computed for

proper TDM configuration as described in TDM_cmax (24h-25h).