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IS25LP064A-RGLA3 数据表(PDF) 20 Page - Integrated Silicon Solution, Inc

部件名 IS25LP064A-RGLA3
功能描述  3V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE
PDF  99 Pages
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制造商  ISSI [Integrated Silicon Solution, Inc]
网页  http://www.issi.com
标志 ISSI - Integrated Silicon Solution, Inc

IS25LP064A-RGLA3 数据表(HTML) 20 Page - Integrated Silicon Solution, Inc

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IS25LP064A/032A
Integrated Silicon Solution, Inc.- www.issi.com
20
Rev. A
11/06/2015
Table 6.10 Read Dummy Cycles vs Max Frequency
Read Modes
P4,P3 = 00
(Default)
P4,P3 = 01
P4,P3 = 10
P4,P3 = 11
Remark
Mode
Normal Read
03h
0
0
0
0
Max. 50MHz
SPI
Fast Read
(2)
0Bh
8
8
8
8
Max. 133MHz
(1)
SPI
6
(104MHz)
4
(84MHz)
8
(1)
(133MHz)
10
(1)
(133MHz)
QPI
Fast Read DTR
0Dh
4
4
4
4
Max.66MHz
SPI
3
(51MHz)
2
(38MHz)
4
(64MHz)
5
(66MHz)
QPI
Fast Read Dual Output
3Bh
8
8
8
8
Max. 133MHz
(1)
SPI
Fast Read Dual IO
BBh
4
(104MHz)
4
(104MHz)
8
(1)
(133MHz)
8
(1)
(133MHz)
SPI
Fast Read Dual IO DTR
BDh
2
(52MHz)
2
(52MHz)
4
(66MHz)
4
(66MHz)
SPI
Fast Read Quad Output
6Bh
8
8
8
8
Max. 133MHz
(1)
SPI
Fast Read Quad IO
EBh
6
(104MHz)
4
(84MHz)
8
(1)
(133MHz)
10
(1)
(133MHz)
SPI , QPI
Fast Read Quad IO DTR
EDh
3
(51MHz)
2
(38MHz)
4
(64MHz)
5
(66MHz)
SPI , QPI
Notes:
1. Max frequency is 133 MHz at Vcc=2.7V~3.6V and 104MHz at Vcc=2.3V~3.6V.
2. RDUID, RDSFDP, IRRD instructions are also applied.
3. Dummy cycles in the table are including Mode bit cycles.
4. Must satisfy bus I/O contention. For instance, if the number of dummy cycles and AX bit cycles are same, then X
must be Hi-Z.
Table 6.11 Driver Strength Table
ODS2
ODS1
ODS0
Description
Remark
0
0
0
Reserved
0
0
1
12.50%
0
1
0
25%
0
1
1
37.50%
1
0
0
Reserved
1
0
1
75%
1
1
0
100%
1
1
1
50%
Default



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