IS25LP064A-RGLA3 datasheet(72/99 Pages) ISSI

72 / 99 page

IS25LP064A/032A

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

11/06/2015

8.37 FAST READ DUAL IO DTR MODE OPERATION (FRDDTR, BDh)

The FRDDTR instruction enables Double Transfer Rate throughput on dual I/O of the device in read mode. The

address (interleave on dual I/O pins) is latched on both rising and falling edge of SCK, and the data (interleave

on dual I/O pins) shift out on both rising and falling edge of SCK at a maximum frequency fT2. The 4-bit address

can be latched-in at one clock, and 4-bit data can be read out at one clock, which means two bits at the rising

edge of clock, the other two bits at the falling edge of clock.

The first address byte can be at any location. The address is automatically increased to the next higher address

after each byte of data is shifted out, so the whole memory can be read out with a single FRDDTR instruction.

The address counter rolls over to 0 when the highest address is reached. Once writing FRDDTR instruction, the

following address/dummy/data out will perform as 4-bit instead of previous 1-bit.

The sequence of issuing FRDDTR instruction is: CE# goes low  Sending FRDDTR instruction (1-bit per clock)

 24-bit address interleave on IO1 & IO0 (4-bit per clock)  2 dummy clocks (configurable default is 2 clocks)

on IO1 & IO0  Data out interleave on IO1 & IO0 (4-bit per clock)  End FRDDTR operation via pulling CE#

high at any time during data out (Please refer to Figure 8.57 for 2 x I/O Double Transfer Rate Read Mode

Timing Waveform).

If AXh (

where X is don’t care) is input for the mode bits during dummy cycles, the device will enter AX read

operation mode which enables subsequent FRDDTR execution skips command code. It saves cycles as

described in Figure 8.58. When the code is different from AXh, the device exits the AX read operation. After

finishing the read operation, device becomes ready to receive a new command. Since the number of dummy

cycles and AX bit cycles are same in this case, X should be Hi-Z to avoid I/O contention.

If the FRDDTR instruction is issued while a Program/Erase/Write Status Register cycle is in progress (WIP=1),

the instruction will be rejected without any effect on the current cycle.

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