IS25LP064A-RGLA3 datasheet(3/99 Pages) ISSI

3 / 99 page

IS25LP064A/032A

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

11/06/2015

GENERAL DESCRIPTION

The IS25LP064A/032A Serial Flash memory offers a versatile storage solution with high flexibility and

performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash are for systems

that require limited space, a low pin count, and low power consumption. The device is accessed through a 4-

wire SPI Interface consisting of a Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip

Enable (CE#) pins, which can also be configured to serve as multi-I/O (see pin descriptions).

The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock

frequencies of up to 133MHz allow for equivalent clock rates of up to 532MHz (133MHz x 4) which equates to

66Mbytes/s of data throughput. The IS25xP series of Flash adds support for DTR (Double Transfer Rate)

commands that transfer addresses and read data on both edges of the clock. These transfer rates can

outperform 16-bit Parallel Flash memories allowing for efficient memory access to support XIP (execute in

place) operation.

The memory array is organized into programmable pages of 256-bytes. This family supports page program

mode where 1 to 256 bytes of data are programmed in a single command. QPI (Quad Peripheral Interface)

supports 2-cycle instruction further reducing instruction times. Pages can be erased in groups of 4Kbyte

sectors, 32Kbyte blocks, 64Kbyte blocks, and/or the entire chip. The uniform sector and block architecture

allows for a high degree of flexibility so that the device can be utilized for a broad variety of applications

requiring solid data retention.

GLOSSARY

Standard SPI

In this operation, a 4-wire SPI Interface is utilized, consisting of Serial Data Input (SI), Serial Data Output (SO),

Serial Clock (SCK), and Chip Enable (CE#) pins. Instructions are sent via the SI pin to encode instructions,

addresses, or input data to the device on the rising edge of SCK. The SO pin is used to read data or to check the

status of the device. This device supports SPI bus operation modes (0,0) and (1,1).

Multi I/O SPI

Multi-I/O operation utilizes an enhanced SPI protocol to allow the device to function with Dual Output, Dual Input

and Output, Quad Output, and Quad Input and Output capability. Executing these instructions through SPI

mode will achieve double or quadruple the transfer bandwidth for READ and PROGRAM operations.

QPI

The device supports Quad Peripheral Interface (QPI) operations only when the device is switched from

Standard/Dual/Quad SPI mode to QPI mode using the enter QPI (35h) instruction. The typical SPI protocol

requires that the byte-long instruction code being shifted into the device only via SI pin in eight serial clocks. The

QPI mode utilizes all four I/O pins to input the instruction code thus requiring only two serial clocks. This can

significantly reduce the SPI instruction overhead and improve system performance. Only QPI mode or

SPI/Dual/Quad mode can be active at any given time. Enter QPI (35h) and Exit QPI (F5h) instructions are used

to switch between these two modes, regardless of the non-volatile Quad Enable (QE) bit status in the Status

SO pins become bidirectional I/O0 and I/O1, and WP# and HOLD# pins become I/O2 and I/O3 respectively

during QPI mode.

DTR

In addition to SPI and QPI features, the device also supports Fast READ DTR operation, which allows high data

throughput while running at lower clock frequencies. DTR READ mode uses both rising and falling edges of the

clock to drive output, resulting in reducing input and output cycles by half.

IS25LP064A-RGLA3 数据表(PDF) 3 Page - Integrated Silicon Solution, Inc

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