RM48L540DPGET datasheet(3/174 Pages) TI

3 / 174 page

RM48L940, RM48L740, RM48L540

www.ti.com

SPNS175C – APRIL 2012 – REVISED JUNE 2015

1.3

Description

The RM48Lx40 device is a high-performance microcontroller family for safety systems. The safety

architecture includes dual CPUs in lockstep, CPU and memory BIST logic, ECC on both the flash and the

data SRAM, parity on peripheral memories, and loopback capability on peripheral I/Os.

The RM48Lx40 device integrates the ARM Cortex-R4F Floating-Point CPU. The CPU offers an efficient

1.66 DMIPS/MHz, and has configurations that can run up to 200 MHz, providing up to 332 DMIPS. The

device supports the little-endian [LE] format.

The RM48L940 device has 3MB of integrated flash and 256KB of data RAM. The RM48L740 device has

2MB of integrated flash and 256KB of data RAM. The RM48L540 device has 2MB of integrated flash and

192KB of data RAM. Both the flash and RAM have single-bit error correction and double-bit error

detection. The flash memory on this device is a nonvolatile, electrically erasable, and programmable

memory implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input

(same level as I/O supply) for all read, program, and erase operations. When in pipeline mode, the flash

operates with a system clock frequency of up to 200 MHz. The SRAM supports single-cycle read and write

accesses in byte, halfword, word, and double-word modes.

The RM48Lx40 device features peripherals for real-time control-based applications, including two Next

Generation High-End Timer (N2HET) timing coprocessors and two 12-bit Analog-to-Digital Converters

(ADCs) supporting up to 24 inputs.

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time

applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer

micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs,

capture or compare inputs, or GPIO. The N2HET is especially well suited for applications requiring

multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer

Transfer Unit (HTU) can perform DMA-type transactions to transfer N2HET data to or from main memory.

A Memory Protection Unit (MPU) is built into the HTU.

The device has two 12-bit-resolution MibADCs with 24 channels and 64 words of parity-protected buffer

RAM each. The MibADC channels can be converted individually or can be grouped by software for

sequential conversion sequences. Sixteen channels are shared between the two MibADCs. There are

three separate groupings. Each sequence can be converted once when triggered or configured for

continuous conversion mode. The MibADC has a 10-bit mode for use when compatibility with older

devices or faster conversion time is desired.

The device has multiple communication interfaces: three MibSPIs, two SPIs, one LIN, one SCI, three

DCANs, one I2C module, and one Ethernet. The SPIs provide a convenient method of serial high-speed

communication between similar shift-register type devices. The LIN supports the Local Interconnect

standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero

(NRZ) format.

The DCAN supports the CAN 2.0 (A and B) protocol standard and uses a serial, multimaster

communication protocol that efficiently supports distributed real-time control with robust communication

rates of up to 1 Mbps. The DCAN is ideal for systems operating in noisy and harsh environments (for

example, automotive vehicle networking and industrial fieldbus) that require reliable serial communication

or multiplexed wiring.

The Ethernet module supports MII, RMII, and MDIO interfaces.

The I2C module is a multimaster communication module providing an interface between the

microcontroller and an I2C-compatible device through the I2C serial bus. The I2C supports speeds of 100

and 400 Kbps.

Device Overview

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