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RM48L540DPGET 数据表(PDF) 21 Page - Texas Instruments |
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RM48L540DPGET 数据表(HTML) 21 Page - Texas Instruments |
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21 / 174 page  RM48L940, RM48L740, RM48L540 www.ti.com SPNS175C – APRIL 2012 – REVISED JUNE 2015 4.3.2 ZWT Package 4.3.2.1 Multibuffered Analog-to-Digital Converters (MibADCs) Table 4-20. ZWT Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2) TERMINAL RESET SIGNAL PULL PULL TYPE DESCRIPTION 337 TYPE SIGNAL NAME STATE ZWT ADREFHI(1) V15 Input ADC high reference supply ADREFLO(1) V16 Input N/A None ADC low reference supply VCCAD(1) W15 Power Operating supply for ADC VSSAD V19 VSSAD W16 Ground N/A None ADC supply power VSSAD W18 VSSAD W19 Programmable, ADC1 event trigger input, or AD1EVT/MII_RX_ER/RMII_RX_ER N19 I/O Pulldown 20 µA GPIO Programmable, ADC2 event trigger input, or MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS V10 I/O Pullup 20 µA GPIO AD1IN[0] W14 AD1IN[1] V17 AD1IN[2] V18 AD1IN[3] T17 Input N/A None ADC1 analog input AD1IN[4] U18 AD1IN[5] R17 AD1IN[6] T19 AD1IN[7] V14 AD1IN[8] / AD2IN[8] P18 AD1IN[9] / AD2IN[9] W17 AD1IN[10] / AD2IN[10] U17 AD1IN[11] / AD2IN[11] U19 AD1IN[12] / AD2IN[12] T16 AD1IN[13] / AD2IN[13] T18 AD1IN[14] / AD2IN[14] R18 AD1IN[15] / AD2IN[15] P19 ADC1/ADC2 shared analog Input N/A None inputs AD1IN[16] / AD2IN[0] V13 AD1IN[17] / AD2IN[1] U13 AD1IN[18] / AD2IN[2] U14 AD1IN[19] / AD2IN[3] U16 AD1IN[20] / AD2IN[4] U15 AD1IN[21] / AD2IN[5] T15 AD1IN[22] / AD2IN[6] R19 AD1IN[23] / AD2IN[7] R16 (1) The ADREFHI, ADREFLO, VCCAD, and VSSAD connections are common for both ADC cores. Copyright © 2012–2015, Texas Instruments Incorporated Terminal Configuration and Functions 21 Submit Documentation Feedback |
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