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RM48L540DPGET 数据表(PDF) 48 Page - Texas Instruments |
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RM48L540DPGET 数据表(HTML) 48 Page - Texas Instruments |
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48 / 174 page  tf tr VCCIO VOH VOH VOL VOL 0 Output RM48L940, RM48L740, RM48L540 SPNS175C – APRIL 2012 – REVISED JUNE 2015 www.ti.com Table 5-7. Switching Characteristics for Output Timings Versus Load Capacitance (CL) (continued) PARAMETER MIN MAX UNIT CL = 15 pF 2.5 CL = 50 pF 4 Rise time, tr CL = 100 pF 7.2 CL = 150 pF 12.5 8 mA mode ns CL = 15 pF 2.5 CL = 50 pF 4 Fall time, tf CL = 100 pF 7.2 CL = 150 pF 12.5 Selectable 8 mA/2 mA-z pins (see Table 5-4) CL = 15 pF 8 CL = 50 pF 15 Rise time, tr CL = 100 pF 23 CL = 150 pF 33 2 mA-z mode ns CL = 15 pF 8 CL = 50 pF 15 Fall time, tf CL = 100 pF 23 CL = 150 pF 33 Figure 5-3. CMOS-Level Outputs Table 5-8. Timing Requirements for Outputs(1) MIN MAX UNIT Delay between low-to-high, or high-to-low transition of general-purpose output td(parallel_out) signals that can be configured by an application in parallel, for example, all signals in 5 ns a GIOA port, or all N2HET1 signals, and so forth. (1) This specification does not account for any output buffer drive strength differences or any external capacitive loading differences. Check Table 5-4 for output buffer drive strength information on each signal. 48 Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback |
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