RM48L540DPGET datasheet(88/174 Pages) TI

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EMIF_nCS[3:2]

Asserted

EMIF_BA[1:0]

EMIF_ADDR[21:0]

EMIF_DATA[15:0]

EMIF_nWE

EMIF_WAIT

SETUP

Extended Due to EMIF_WAIT

Deasserted

STROBE

STROBE HOLD

RM48L940, RM48L740, RM48L540

SPNS175C – APRIL 2012 – REVISED JUNE 2015

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Figure 6-16. EMIFnWAIT Write Timing Requirements

Table 6-27. EMIF Asynchronous Memory Timing Requirements

NO.

MIN

NOM

MAX

UNIT

READS AND WRITES

EMIF clock period

Pulse duration, EMIFnWAIT

tw(EM_WAIT)

assertion and deassertion

READS

tsu(EMDV-EMOEH)

Setup time, EMIFDATA[15:0]

valid before EMIFnOE high

th(EMOEH-EMDIV)

Hold time, EMIFDATA[15:0] valid

0.5

after EMIFnOE high

Setup Time, EMIFnWAIT

tsu(EMOEL-EMWAIT)

asserted before end of Strobe

4E+30

Phase(1)

WRITES

Setup Time, EMIFnWAIT

tsu(EMWEL-EMWAIT)

asserted before end of Strobe

4E+30

Phase(1)

(1)

Setup before end of STROBE phase (if no extended wait states are inserted) by which EMIFnWAIT must be asserted to add extended

wait states. Figure 6-14 and Figure 6-16 describe EMIF transactions that include extended wait states inserted during the STROBE

phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where

the HOLD phase would begin if there were no extended wait cycles.

System Information and Electrical Specifications

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RM48L540DPGET 数据表(PDF) 88 Page - Texas Instruments

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