Symbol

Parameter

Test condition

Min

Typ

Max

Unit

FSET

Sensing offset

-15

+15

mV

Total OFF time

9

µs

125

µs

Internal oscillator precision

-20%

+20%

2%

W

Slow decay time

5/8 ×

µs

T

Fast decay time

3/8 ×

µs

Logic IOs

High logic level input voltage

1.6

V

Low logic level input voltage

0.6

V

E

FAULT open drain release

voltage

0.4

V

EN Low logic level output

voltage

0.4

V

STBY pull-down resistance

36

kΩ

EN pull-down current

10.5

µA

EN input propagation delay

From EN falling edge to OUT high

impedance

55

ns

From STBY edge, see Figure 6

100

µs

From STBY edge, see Figure 6

1

µs

DIR input hold time

From STCK rising edge, see Figure 5

100

ns

DIR input setup time

From STCK rising edge, see Figure 5

100

ns

See Figure 5

100

ns

STCK low time

See Figure 5

100

ns

STCK inputs frequency

See Figure 5

1

MHz

Protections

Thermal shutdown threshold

160

°C

40

°C

Overcurrent threshold

See Figure 15. Power stage resistance

versus temperature

2

A

1. Based on characterization data on a limited number of samples, not tested during production.

STSPIN220

Electrical characteristics

DS11633 - Rev 4

page 6/27