August 2004

ASM5CVF857

rev 1.2

2.5V Wide-Range Frequency Clock Driver (60 MHz

– 200 MHz)

11 of 15

Notice: The information in this document is subject to change without notice.

Y

Y

X

, FB_OUTT

Y

X

Y

X

t

(skew)

Figure 6: Output Skew

t

half period n+1

n = any half cycle

Figure 8: Half-Period Jitter

Y , FB_OUTC

Y

Y

Y

t

c(n)

Figure 7: Period Jitter

X

CLK_INC

CLK_INT

FB_INC

FB_INT

(N > 1000 samples)

Figure 5: Static Phase Offset

80%

Clock inputs and outputs

Figure 9: Input and Output Slew rates

20%

t

t

80%

20%