August 2004

ASM5CVF857

rev 1.2

2.5V Wide-Range Frequency Clock Driver (60 MHz

– 200 MHz)

9 of 15

Notice: The information in this document is subject to change without notice.

Switching Characteristics**

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Low-to-high level propagation delay time

*

CLK_IN to any output

3.5

ns

High-to-low level propagation delay time

*

CLK_IN to any output

3.5

ns

Output enable time

PDB to any output

3

ns

Output disable time

PDB to any output

3

ns

Period Jitter

100MHz to 200MHz

-30

30

ps

Half-period jitter

100MHz to 200MHz

-75

75

ps

Input clock slew rate

1

4

v/ns

Output clock slew rate

100/133/167/200 MHz

1

2

v/ns

Cycle-to-cycle jitter

100 MHz to 200MHz

-50

50

ps

Static phase offset

#

-50

0

50

ps

Output-to-output skew

40

60

ps

The PLL on the ASM5CVF857 is capable of meeting all the above parameters while supporting SSC synthesizers with

the following parameters.

SSC modulation frequency

30.00

50.00

kHz

SSC clock input frequency deviation

0.00

-0.50

%

PLL loop bandwidth

2

MHz

Phase angle

-0.031

°

*: Refers to transition on non-inverting output in PLL bypass mode.

#: Static phase offset does not include jitter.

Note: While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This

Note: Switching characteristics guaranteed for application frequency range.