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BQ27Z561-R2 数据表(PDF) 8 Page - Texas Instruments |
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BQ27Z561-R2 数据表(HTML) 8 Page - Texas Instruments |
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8 / 22 page  PARAMETER TEST CONDITIONS MIN NOM MAX UNIT tf Clock fall time 90% to 10% 300 ns tSU:STO Setup time STOP condition 4.0 µs tBUF Bus free time STOP to START 4.7 µs 7.18 I2C Timing — 400 kHz PARAMETER TEST CONDITIONS MIN NOM MAX UNIT fSCL Clock operating frequency SCL duty cycle = 50% 400 kHz tHD:STA START condition hold time 0.6 µs tLOW Low period of the SCL Clock 1.3 µs tHIGH High period of the SCL Clock 600 ns tSU:STA Setup repeated START 600 ns tHD:DAT Data hold time (SDA input) 0 ns tSU:DAT Data setup time (SDA input) 100 ns tr Clock rise time 10% to 90% 300 ns tf Clock fall time 90% to 10% 300 ns tSU:STO Setup time STOP condition 0.6 µs tBUF Bus free time STOP to START 1.3 µs 7.19 HDQ Timing PARAMETER TEST CONDITIONS MIN NOM MAX UNIT tB Break time 190 µs tBR Break recovery time 40 µs tHW1 Host write 1 time Host drives HDQ 0.5 50 µs tHW0 Host write 0 time Host drives HDQ 86 145 µs tCYCH Cycle time, host to device Device drives HDQ 190 µs tCYCD Cycle time, device to Host Device drives HDQ 190 205 250 µs tDW1 Device write 1 time Device drives HDQ 32 50 µs tDW0 Device write 0 time Device drives HDQ 80 145 µs tRSPS Device response time Device drives HDQ 190 950 µs tTRND Host turn around time Host drives HDQ after device drives HDQ 250 µs tRISE HDQ line rising time to logic 1 1.8 µs tRST HDQ Reset Host drives HDQ low before device reset 2.2 s SCL SDA tHD;STA tLOW tr tHD;DAT tHIGH tf tSU;DAT tSU;STA tSU;STO tf START REPEATED START STOP tHD;STA START tSP tr tBUF Figure 7-1. I2C Timing BQ27Z561-R2 SLUSE22 – SEPTEMBER 2020 www.ti.com 8 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: BQ27Z561-R2 |
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