IIS2MDC datasheet(24/40 Pages) STMICROELECTRONICS

24 / 40 page

Digital interfaces

IIS2MDC

24/40

DocID030986 Rev 1

(MSb) first. If a receiver can’t receive another complete byte of data until it has performed

some other function, it can hold the clock line SCL low to force the transmitter into a wait

state. Data transfer only continues when the receiver is ready for another byte and releases

the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to

receive because it is performing some real-time function) the data line must be left high by

the slave. The master can then abort the transfer. A low-to-high transition on the SDA line

while the SCL line is high is defined as a STOP condition. Each data transfer must be

terminated by the generation of a STOP (SP) condition.

In the presented communication format MAK is Master acknowledge and NMAK is No

Master Acknowledge.

Default address:

The slave address is 0011110b.

The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated

START (SR) condition must be issued after the sub-address byte. If the bit is ‘0’ (Write) the

master will transmit to the slave with direction unchanged. Table 21 explains how the

SAD+Read/Write bit patterns are composed, listing all the possible configurations.

Table 21. SAD + Read/Write patterns

Command

SAD[6:0]

R/W

SAD + R/W

Read

0011110

00111101 (3Dh)

Write

0011110

00111100 (3Ch)

IIS2MDC 数据表(PDF) 24 Page - STMicroelectronics