IIS2MDC datasheet(30/40 Pages) STMICROELECTRONICS

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IIS2MDC

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DocID030986 Rev 1

8.5

CFG_REG_A (60h)

The configuration register is used to configure the output data rate and the measurement

configuration.

Table 23. CFG_REG_A register

COMP_

TEMP_EN

REBOOT

SOFT_RST

ODR1

ODR0

MD1

MD0

Table 24. CFG_REG_A register description

COMP_

TEMP_EN(1)

1. For proper operation, this bit must be set to '1'.

Enables the magnetometer temperature compensation. Default value: 0

(0: temperature compensation disabled; 1: temperature compensation enabled)

REBOOT

Reboot magnetometer memory content. Default value: 0

(0: normal mode; 1: reboot memory content)

SOFT_RST

When this bit is set, the configuration registers and user registers are reset.

Flash registers keep their values. Default value: 0

Enables low-power mode. Default value: 0

0: high-resolution mode 1: low-power mode enabled

ODR[1:0]

Output data rate configuration (see Table 25: Output data rate configuration).

Default value: 00

MD[1:0]

These bits select the mode of operation of the device (see Table 26: Mode of

operation). Default value: 11

Table 25. Output data rate configuration

ODR1

ODR0

ODR (Hz)

10 (default)

100

Table 26. Mode of operation

MD1

MD0

Mode

Continuous mode. In continuous mode the device continuously performs

measurements and places the result in the data register. The data-ready

signal is generated when a new data set is ready to be read. This signal can

be available on the external pin by setting the DRDY_on_PIN bit in

CFG_REG_C (62h).

Single mode. When single mode is selected, the device performs a single

measurement, sets DRDY high and returns to idle mode. Mode register

return to idle mode bit values.

Idle mode. Device is placed in idle mode. I2C and SPI active.

Idle mode. Device is placed in idle mode. I2C and SPI active (default).

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