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MAS3549F 数据表(PDF) 13 Page - Micronas

部件名 MAS3549F
功能描述  MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec
PDF  92 Pages
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制造商  MICRONAS [Micronas]
网页  http://www.micronas.com
标志 MICRONAS - Micronas

MAS3549F 数据表(HTML) 13 Page - Micronas

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DATA SHEET
MAS 35x9F
Micronas
June 30, 2004; 6251-505-1DS
13
2.6.3. Power Supply Configurations
One of the following supply configurations may be
used:
– Power-optimized solution (recommended opera-
tion). DC/DC 1 (e.g. 2.2 V) drives the MAS 35x9F
DSP and the audio circuitry, DC/DC 2 (e.g. 2.7 V)
supplies controller and flash (see Fig. 2–8 on
page 14)
– Volume-optimized solution. DC/DC 1 (e.g. 2.7 V)
supplies controller, flash and MAS 35x9F audio
parts, DC/DC 2 generates e.g. 2.2 V for the
MAS 35x9F DSP (see Fig. 2–9 on page 14).
– Minimized external components. DC/DC 1 operates
on, e.g., 2.7 V and feeds all components, DC/DC 2
remains off (see Fig. 2–10 on page 14).
– External power supply. All components are powered
by an external source, no DC/DC converter is used
(see Fig. 2–11 on page 14).
If DC/DC converter 1 is used, it must supply the analog
circuits (pins AVDD0, AVDD1) of the MAS 35x9F.
If only one DC/DC converter is required, DC/DC1 must
be used. Pin DCSO2 must be left vacant, pin VSENS2
should be connected to pin VSENS1.
If the DC/DC converters are not used, pin DCEN must
be connected to VSS, DCSOx must be left vacant.
Fig. 2–7: DC/DC converter overview. The DCEN input must be connected to pin I2CVDD via start-up push button.
15
8
+
+
VSS
DCSO2
DCSG2
DCEN
PUP
VSENS2
Vin
22
µH
C1
330
µF
S
R
30
DCFR (77hex)
DCCF (76hex)
70
DCCF (76hex)
D1
Start
PUP2
set voltage
factor
output 1
I2CVDD
to I2C interface
supply
L1
VBAT
battery
voltage
monitor
DC/DC
converter 2
voltage
monitor
voltage
monitor
DC/DC
converter 1
frequency
divider
system
or crystal
clock
+



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