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XIO2001IPNP 数据表(PDF) 79 Page - Texas Instruments |
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XIO2001IPNP 数据表(HTML) 79 Page - Texas Instruments |
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79 / 144 page  79 XIO2001 www.ti.com SCPS212I – MAY 2009 – REVISED JANUARY 2016 Product Folder Links: XIO2001 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Table 49. General Control Register Description (continued) BIT FIELD NAME ACCESS DESCRIPTION 9:8(1) MIN_POWER_S CALE RW Minimum power scale. This value is programmed to indicate the scale of bits 7:0 (MIN_POWER_VALUE). 00 = 01 = 10 = 11 = 1.0x 0.1x 0.01x (default) 0.001x 7:0(1) MIN_POWER_VA LUE RW Minimum power value. This value is programmed to indicate the minimum power requirements. This value is multiplied by the minimum power scale field (bits 9:8) to determine the minimum power requirements for the bridge. The default is 5Fh, indicating that the bridge requires 0.95 W of power. This field can be reprogrammed through an EEPROM or the system BIOS. 8.4.67 Clock Control Register This register enables and disables the PCI clock outputs (CLKOUT). See Table 50 for a complete description of the register contents. PCI register offset: D8h Register type: Read-only, Read/Write Default value: 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 (1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset. Table 50. Clock Control Register Description BIT FIELD NAME ACCESS DESCRIPTION 7(1) RSVD R Reserved. Returns 0b when read. 6(1) CLOCK6_DISABLE RW Clock output 6 disable. This bit disables secondary CLKOUT6. 0 = Clock enabled (default) 1 = Clock disabled 5(1) CLOCK5_DISABLE RW Clock output 5 disable. This bit disables secondary CLKOUT5. 0 = Clock enabled (default) 1 = Clock disabled 4(1) CLOCK4_DISABLE RW Clock output 4 disable. This bit disables secondary CLKOUT4. 0 = Clock enabled (default) 1 = Clock disabled 3(1) CLOCK3_DISABLE RW Clock output 3 disable. This bit disables secondary CLKOUT3. 0 = Clock enabled (default) 1 = Clock disabled 2(1) CLOCK2_DISABLE RW Clock output 2 disable. This bit disables secondary CLKOUT2. 0 = Clock enabled (default) 1 = Clock disabled 1(1) CLOCK1_DISABLE RW Clock output 1 disable. This bit disables secondary CLKOUT1. 0 = Clock enabled (default) 1 = Clock disabled 0(1) CLOCK0_DISABLE RW Clock output 0 disable. This bit disables secondary CLKOUT0. 0 = Clock enabled (default) 1 = Clock disabled |
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