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XIO2001IPNP 数据表(PDF) 13 Page - Texas Instruments |
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XIO2001IPNP 数据表(HTML) 13 Page - Texas Instruments |
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13 / 144 page  13 XIO2001 www.ti.com SCPS212I – MAY 2009 – REVISED JANUARY 2016 Product Folder Links: XIO2001 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Pin Functions (continued) SIGNAL ZGU BALL NO. ZAJ BALL NO. PNP PIN NO. I/O TYPE CELL TYPE CLAMP RAIL EXTERNAL PARTS DESCRIPTION JTAG_TRST L09 L09 60 I LV CMOS VDD_33 Optional pullup resistor JTAG test reset. This terminal provides Optional for asynchronous initialization of the TAP controller. Note: This terminal has an internal active pullup resistor. The pullup is active at all times. Note: This terminal should be tied to ground or pulled low if JTAG is not required. Miscellaneous Pins SIGNAL ZGU BALL NO. ZAJ BALL NO. PNP PIN NO. I/O TYPE CELL TYPE CLAMP RAIL EXTERNAL PARTS DESCRIPTION CLKRUN_ EN A13 C11 96 I LV CMOS VDD_33 Optional pullup/ pulldown resistor Clock run enable 0 = Clock run support disabled 1 = Clock run support enabled EXT_ARB_EN C10 A12 97 I LV CMOS VDD_33 Optional pullup/ pulldown resistor External arbiter enable 0 = Internal arbiter enabled 1 = External arbiter enabled GPIO0 // CLKRUN N09 N09 55 I/O LV CMOS VDD_33 Optional pullup resistor General-purpose I/O 0/clock run. This terminal functions as a GPIO controlled by bit 0 (GPIO0_DIR) in the GPIO control register (see GPIO Control Register) or the clock run terminal. This terminal is used as clock run input when the bridge is placed in clock run mode. Note: In clock run mode, an external pullup resistor is required to prevent the CLKRUN signal from floating. Note: This terminal has an internal active pullup resistor. The pullup is only active when reset is asserted or when the GPIO is configured as an input. GPIO1 // PWR_ OVRD M09 M09 56 I/O LV CMOS VDD_33 – General-purpose I/O 1/power override. This terminal functions as a GPIO controlled by bit 1 (GPIO1_DIR) in the GPIO control register (see GPIO Control Register) or the power override output terminal. GPIO1 becomes PWR_OVRD when bits 22:20 (POWER_OVRD) in the general control register are set to 001b or 011b (see General Control Register). Note: This terminal has an internal active pullup resistor. The pullup is only active when reset is asserted or when the GPIO is configured as an input. GPIO2 N10 N10 57 I/O LV CMOS VDD_33 – General-purpose I/O 2. This terminal functions as a GPIO controlled by bit 2 (GPIO2_DIR) in the GPIO control register (see GPIO Control Register). Note: This terminal has an internal active pullup resistor. The pullup is only active when reset is asserted or when the GPIO is configured as an input. |
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