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XIO2001IPNP 数据表(PDF) 90 Page - Texas Instruments |
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XIO2001IPNP 数据表(HTML) 90 Page - Texas Instruments |
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90 / 144 page  90 XIO2001 SCPS212I – MAY 2009 – REVISED JANUARY 2016 www.ti.com Product Folder Links: XIO2001 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated (1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset. Table 60. Cache Timer Transfer Limit Register Description BIT FIELD NAME ACCESS DESCRIPTION 15:8 RSVD R Reserved. Returns 00h when read. 7:0(1) CACHE_TMR_XFR _LIMIT RW Number of PCI cycle starts that have to occur without a read hit on the completion data buffer, before the cache data can be discarded. 8.4.78 Cache Timer Lower Limit Register Minimum number of clock cycles that must have passed without a read hit on the completion data buffer before the "cache miss limit" check can be triggered. See Table 61 for a complete description of the register contents. PCI register offset: ECh Register type: Read/Clear Default value: 007Fh BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 (1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset. Table 61. Cache Timer Lower Limit Register Description BIT FIELD NAME ACCESS DESCRIPTION 15:12 RSVD R Reserved. Returns 0h when read. 11:0(1) CACHE_TIMER _LOWER_LIMIT RW Minimum number of clock cycles that must have passed without a read hit on the completion data buffer before the "cache miss limit" check can be triggered. 8.4.79 Cache Timer Upper Limit Register Discard cached data after this number of clock cycles have passed without a read hit on the completion data buffer. See Table 62 for a complete description of the register contents. PCI register offset: EEh Register type: Read/Clear Default value: 01C0h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 (1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset. Table 62. Cache Timer Upper Limit Register Description BIT FIELD NAME ACCESS DESCRIPTION 15:12 RSVD R Reserved. Returns 0h when read. 11:0(1) CACHE_TIMER _UPPER_LIMIT RW Discard cached data after this number of clock cycles have passed without a read hit on the completion data buffer. |
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