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XIO2001IPNP 数据表(PDF) 21 Page - Texas Instruments |
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XIO2001IPNP 数据表(HTML) 21 Page - Texas Instruments |
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21 / 144 page  21 XIO2001 www.ti.com SCPS212I – MAY 2009 – REVISED JANUARY 2016 Product Folder Links: XIO2001 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated (1) The PCI shared signals are AD31:0, C/BE[3:0], FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, LOCK, SERIRQ, PAR, PERR, SERR, and CLKRUN. 6.11 PCI Bus Timing Requirements over recommended operating conditions (1) PARAMETER TEST CONDITION 33 MHz 66 MHz UNIT MIN MAX MIN MAX tpd CLK to shared signal valid propagation delay time CL = 50 pF 11 ns CL = 30 pF 6 CLK to shared signal invalid propagation delay time CL = 50 pF 2 CL = 30 pF 1 tON tEnable time, high-impedance-to-active delay time from CLK CL = 50 pF 2 ns CL = 30 pF 1 tOFF Disable time, active-to-high-impedance delay time from CLK CL = 50 pF 28 ns CL = 30 pF 14 tsu Setup time on shared signals before CLK valid (rising edge) 7 3 ns th Hold time on shared signals after CLK valid (rising edge) 0 0 ns 6.12 Power-Up/-Down Sequencing The bridge contains both 1.5-V and 3.3-V power terminals. The following power-up and power-down sequences describe how power is applied to these terminals. In addition, the bridge has three resets: PERST, GRST and an internal power-on reset. These resets are fully described in Bridge Reset Features. The following power-up and power-down sequences describe how PERST is applied to the bridge. The application of the PCI Express reference clock (REFCLK) is important to the power-up/-down sequence and is included in the following power-up and power-down descriptions. 6.12.1 Power-Up Sequence 1. Assert GRST and PERST to the device. 2. Apply 1.5-V and 3.3-V voltages. 3. Deassert GRST. 4. Apply a stable PCI Express reference clock. 5. To meet PCI Express specification requirements, PERST cannot be deasserted until the following two delay requirements are satisfied: – Wait a minimum of 100 μs after applying a stable PCI Express reference clock. The 100-μs limit satisfies the requirement for stable device clocks by the deassertion of PERST. – Wait a minimum of 100 ms after applying power. The 100-ms limit satisfies the requirement for stable power by the deassertion of PERST. See the power-up sequencing diagram in Figure 4. |
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