STM32H747AI datasheet(8/252 Pages) STMICROELECTRONICS

8 / 252 page

List of tables

STM32H747xI/G

2/242

DS12930 Rev 1

running from Flash memory, only Arm Cortex-M7 running, cache ON,

LDO regulator ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 38.

Typical and maximum current consumption in Run mode, code with data processing

running from Flash memory, only Arm Cortex-M7 running, cache OFF,

LDO regulator ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 39.

Typical and maximum current consumption batch acquisition mode,

LDO regulator ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 40.

Typical and maximum current consumption in Run mode, code with data processing

running from Flash memory, only Arm Cortex-M4 running, ART accelerator ON,

LDO regulator ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 41.

Typical and maximum current consumption in Run mode, code with data processing

running from Flash bank 2, only Arm Cortex-M4 running, ART accelerator ON,

SMPS regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 42.

Typical and maximum current consumption in Stop, LDO regulator ON . . . . . . . . . . . . . 115

Table 43.

Typical and maximum current consumption in Stop, SMPS regulator . . . . . . . . . . . . . . . 116

Table 44.

Typical and maximum current consumption in Sleep mode, LDO regulator . . . . . . . . . . 117

Table 45.

Typical and maximum current consumption in Sleep mode, SMPS regulator . . . . . . . . . 117

Table 46.

Typical and maximum current consumption in Standby . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 47.

Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 118

Table 48.

Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 49.

Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 50.

High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 51.

Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 52.

4-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 53.

Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 54.

HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 55.

HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 56.

CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 57.

LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 58.

PLL characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 59.

PLL characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Table 60.

MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Table 61.

MIPI D-PHY AC characteristics LP mode and HS/LP

transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 62.

DSI regulator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 63.

Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Table 64.

Flash memory programming (single bank configuration nDBANK=1) . . . . . . . . . . . . . . . 141

Table 65.

Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 66.

EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 67.

EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Table 68.

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 69.

Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 70.

I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Table 71.

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 72.

Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 . . . . . . . . 148

Table 73.

Output voltage characteristics for PC13, PC14, PC15 and PI8 . . . . . . . . . . . . . . . . . . . . 149

Table 74.

Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 75.

Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 76.

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 77.

Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 155

Table 78.

Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 155

Table 79.

Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 157

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