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H8/3002 数据表(PDF) 20 Page - Renesas Technology Corp |
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H8/3002 数据表(HTML) 20 Page - Renesas Technology Corp |
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20 / 700 page ![]() 1.2 Block Diagram Figure 1-1 shows an internal block diagram. Figure 1-1 Block Diagram Data bus Port 4 A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 P9 5/SCK1/IRQ5 P9 4/SCK0/IRQ4 P9 3/RxD1 P9 2/RxD0 P9 1/TxD1 P9 0/TxD0 Port 7 Port A Port B P8 4/CS0 P8 3/CS1/IRQ3 P8 2/CS2/IRQ2 P8 1/CS3/IRQ1 P8 0/RFSH/IRQ0 P6 2/BACK P6 1/BREQ P6 0/WAIT MD 2 MD 1 MD 0 EXTAL XTAL ø STBY RES RESO NMI LWR HWR RD AS H8/300H CPU Clock osc. Interrupt controller RAM 512 bytes 16-bit integrated timer unit (ITU) Programmable timing pattern controller (TPC) DMA controller (DMAC) Serial communication interface (SCI) 2 channels × A/D converter Watchdog timer (WDT) Refresh controller 5 |
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