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TSZ181ILT 数据表(PDF) 5 Page - STMicroelectronics |
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TSZ181ILT 数据表(HTML) 5 Page - STMicroelectronics |
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5 / 43 page ![]() Symbol Parameter Conditions Min. Typ. Max. Unit en Equivalent input noise voltage density f = 1 kHz 50 nV/√Hz f = 10 kHz 50 en-pp Voltage noise f = 0.1 to 10 Hz 0.6 µVpp Cs Channel separation f = 1 kHz 120 dB tinit Initialization time, G = 100 (4) T = 25 °C 60 µs -40 °C < T< 125 °C 100 1. See Section 5.5 Input offset voltage drift over temperature. Input offset measurements are performed on x100 gain configuration. The amplifiers and the gain setting resistors are at the same temperature. 2. Guaranteed by design. 3. Slew rate value is calculated as the average between positive and negative slew rates. 4. Initialization time is defined as the delay between the moment when supply voltage exceeds 2.2 V and output voltage stabilization Table 4. Electrical characteristics at VCC+ = 3.3 V with VCC- = 0 V, Vicm = VCC/2, T = 25 °C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Unit DC performance Vio Input offset voltage T = 25 °C 2 30 µV -40 °C < T< 125 °C 40 ΔVio/ΔT Input offset voltage drift (1) -40 °C < T< 125 °C 0.1 µV/°C Iib Input bias current (Vout = VCC/2) T = 25 °C 30 200 (2) pA -40 °C < T< 125 °C 300 (2) Iio Input offset current (Vout = VCC/2) T = 25 °C 60 400 (2) -40 °C < T< 125 °C 600 (2) CMR1 Common mode rejection ratio, 20 log (ΔVicm/ ΔVio), Vout = VCC/2, RL > 1 MΩ Vic = 0 V to VCC, T = 25 °C 104 120 dB Vic = 0 V to VCC, -40 °C < T< 125 °C 102 CMR2 Common mode rejection ratio, 20 log (ΔVicm/ ΔVio), Vout = VCC/2, RL > 1 MΩ Vic = 0 V to VCC - 1.8 V, T = 25 °C 106 132 Vic = 0 V to VCC - 2 V, -40 °C < T< 125 °C 106 Avd Large signal voltage gain, Vout = 0.5 V to (VCC - 0.5 V) T = 25 °C 120 138 -40 °C < T< 125 °C 110 VOH High-level output voltage, VOH = Vcc - Vout T = 25 °C 16 40 mV -40 °C < T< 125 °C 70 VOL Low-level output voltage T = 25 °C 11 30 -40 °C < T< 125 °C 70 TSZ181, TSZ182 Electrical characteristics DS11863 - Rev 5 page 5/43 |
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