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TSZ181ILT 数据表(PDF) 21 Page - STMicroelectronics |
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TSZ181ILT 数据表(HTML) 21 Page - STMicroelectronics |
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21 / 43 page ![]() Figure 54. Test configuration for Riso Cload VIN + - +VCC Riso 10 kΩ -VCC VOUT Note that the resistance Riso is in series with Rload and thus acts as a voltage divider, and reduces the output swing a little. Thanks to the natural good stability of TSZ18x, the Riso needed to keep the system stable when the capacitive load exceeds 200pF is lower than 50 Ω (VCC = 5 V), and so the error introduced is generally negligible. The Riso also modifies the open loop gain of the circuit, and tends to improve the phase margin as described in Table 6. Riso impact on stability. Table 6. Riso impact on stability Capacitive load 100 pF 1 nF 10 nF 100 nF 1 µF Riso (Ω) 0 100 47 100 22 47 8 13 10 6 Measured overshoot (%) 20.9 15 23 9 16 8 21 10 12 8 Estimated phase margin (°) 47 53 46 59 52 61 47 58 56 61 5.7 PCB layout recommendations Particular attention must be paid to the layout of the PCB tracks connected to the amplifier, load and power supply. It is good practice to use short and wide PCB traces to minimize voltage drops and parasitic inductance. To minimize parasitic impedance over the entire surface, a multi-via technique that connects the bottom and top layer ground planes together in many locations is often used. The copper traces that connect the output pins to the load and supply pins should be as wide as possible to minimize trace resistance. A ground plane generally helps to reduce EMI, which is why it is generally recommended to use a multilayer PCB and use the ground plane as a shield to protect the internal track. In this case, pay attention to separate the digital from the analog ground and avoid any ground loop. Place external components as close as possible to the op amp and keep the gain resistances, Rf and Rg, close to the inverting pin to minimize parasitic capacitances. 5.8 Optimized application recommendation The TSZ18x is based on a chopper architecture. As the device includes internal switching circuitry, it is strongly recommended to place a 0.1 µF capacitor as close as possible to the supply pins. A good decoupling has several advantages for an application. First, it helps to reduce electromagnetic interference. Due to the modulation of the chopper, the decoupling capacitance also helps to reject the small ripple that may appear on the output. The TSZ18x has been optimized for use with 10 kΩ in the feedback loop. With this, or a higher value resistance, this device offers the best performance. TSZ181, TSZ182 PCB layout recommendations DS11863 - Rev 5 page 21/43 |
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