TSZ181ILT datasheet(41/43 Pages) STMICROELECTRONICS

41 / 43 page

List of figures

Figure 1.

Pin connections for each package (top view) ............................................... 2

Figure 2.

Supply current vs. supply voltage ....................................................... 9

Figure 3.

Input offset voltage distribution at VCC = 5 V ................................................ 9

Figure 4.

Input offset voltage distribution at VCC = 3.3 V .............................................. 9

Figure 5.

Input offset voltage distribution at VCC = 2.2 V .............................................. 9

Figure 6.

Input offset voltage distribution at VCC = 5 V, T = 125 °C ....................................... 9

Figure 7.

Input offset voltage distribution at VCC = 5 V, T = -40 °C........................................ 9

Figure 8.

Input offset voltage distribution at VCC = 2.2 V, T = 125 °C ..................................... 10

Figure 9.

Input offset voltage distribution at VCC = 2.2 V, T = -40 °C ..................................... 10

Figure 10.

Input offset voltage vs. supply voltage ................................................... 10

Figure 11.

Input offset voltage vs. input common-mode at VCC = 5.5 V .................................... 10

Figure 12.

Input offset voltage vs. input common-mode at VCC = 3.3 V .................................... 10

Figure 13.

Input offset voltage vs. input common-mode at VCC = 2.2 V .................................... 10

Figure 14.

Input offset voltage vs. temperature..................................................... 11

Figure 15.

VOH vs. supply voltage ............................................................. 11

Figure 16.

VOL vs. supply voltage.............................................................. 11

Figure 17.

Output current vs. output voltage at VCC = 5.5 V ............................................ 11

Figure 18.

Output current vs. output voltage at VCC = 2.2 V ............................................ 11

Figure 19.

Input bias current vs. common-mode at VCC = 5 V .......................................... 11

Figure 20.

Input bias current vs. temperature at VCC = 5 V ............................................ 12

Figure 21.

Output rail linearity ................................................................ 12

Figure 22.

Bode diagram at VCC = 5.5 V ......................................................... 12

Figure 23.

Bode diagram at VCC = 2.2 V ......................................................... 12

Figure 24.

Bode diagram at VCC = 3.3 V ......................................................... 12

Figure 25.

Open loop gain vs. frequency ......................................................... 12

Figure 26.

Positive slew rate vs. supply voltage .................................................... 13

Figure 27.

Negative slew rate vs. supply voltage ................................................... 13

Figure 28.

Noise 0.1 - 10 Hz vs. time ........................................................... 13

Figure 29.

Noise vs. frequency................................................................ 13

Figure 30.

Noise vs. frequency and temperature ................................................... 13

Figure 31.

Output overshoot vs. load capacitance .................................................. 13

Figure 32.

Small signal VCC = 5 V ............................................................. 14

Figure 33.

Small signal VCC = 2.2 V ............................................................ 14

Figure 34.

Large signal VCC = 5 V ............................................................. 14

Figure 35.

Large signal VCC = 2.2 V ............................................................ 14

Figure 36.

Negative overvoltage recovery VCC = 2.2 V ............................................... 14

Figure 37.

Positive overvoltage recovery VCC = 2.2 V ................................................ 14

Figure 38.

Output impedance vs. frequency....................................................... 15

Figure 39.

Settling time positive step (-2 V to 0 V)................................................... 15

Figure 40.

Settling time negative step (2 V to 0 V) .................................................. 15

Figure 41.

Settling time positive step (-0.8 V to 0 V) ................................................. 15

Figure 42.

Settling time negative step (0.8 V to 0 V) ................................................. 15

Figure 43.

Maximum output voltage vs. frequency .................................................. 15

Figure 44.

Crosstalk vs. frequency ............................................................. 16

Figure 45.

PSRR vs. frequency ............................................................... 16

Figure 46.

Block diagram in the time domain (step 1) ................................................ 17

Figure 47.

Block diagram in the time domain (step 2) ................................................ 17

Figure 48.

Vio cancellation principle ............................................................ 18

Figure 49.

Block diagram in the frequency domain .................................................. 18

TSZ181, TSZ182

List of figures

DS11863 - Rev 5

page 41/43

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