ADP7118

Data Sheet

Rev. F | Page 16 of 24

NOISE REDUCTION OF THE ADP7118 IN

ADJUSTABLE MODE

The ultralow output noise of the ADP7118 is achieved by keeping

the LDO error amplifier in unity gain and setting the reference

voltage equal to the output voltage. This architecture does not

work for an adjustable output voltage LDO in the conventional

sense. However, the ADP7118 architecture allows any fixed

output voltage to be set to a higher voltage with an external

voltage divider. For example, a fixed 5 V output can be set to a

10 V output according to Equation 3 (see Figure 50):

The disadvantage in using the ADP7118 in this manner is that

the output voltage noise is proportional to the output voltage.

Therefore, it is best to choose a fixed output voltage that is close

to the target voltage to minimize the increase in output noise.

The adjustable LDO circuit can be modified to reduce the

output voltage noise to levels close to that of the fixed output

ADP7118. The circuit shown in Figure 50 adds two additional

the error amplifier is approximately 0.1 dB to 0.8 dB. The actual

This gain ensures that the error amplifier always operates at

slightly greater than unity gain.

at a frequency between 1 Hz and 50 Hz. This setting places the

frequency where the ac gain of the error amplifier is 3 dB down

from the dc gain.

VOUT

VIN

GND

SENSE/ADJ

EN

100k

Ω

200k

Ω

2.2µF

2.2µF

ON

OFF

10k

Ω

R2

100k

Ω

+

+

R1

100k

Ω

1µF

+

Figure 50. Noise Reduction Modification

The noise of the adjustable LDO is found by using the

following formula, assuming the noise of a fixed output LDO is

approximately 11 μV.

(9)

Based on the component values shown in Figure 50, the ADP7118

has the following characteristics:

•

DC gain of 10 (20 dB)

•

3 dB roll-off frequency of 1.75 Hz

•

High frequency ac gain of 1.099 (0.82 dB)

•

Theoretical noise reduction factor of 9.1 (19.2 dB)

•

Measured rms noise of the adjustable LDO without noise

reduction is 70 µV rms

•

Measured rms noise of the adjustable LDO with noise

reduction is 12 µV rms

•

Measured noise reduction of approximately 15.3 dB

Note that the measured noise reduction is less than the theoretical

noise reduction. Figure 51 shows the noise spectral density of an

adjustable ADP7118 set to 6 V and 12 V with and without the

noise reduction network. The output noise with the noise

reduction network is approximately the same for both voltages,

especially beyond 100 Hz. The noise of the 6 V and 12 V outputs

without the noise reduction network differs by a factor of 2 up to

approximately 20 kHz. Above 40 kHz, the closed loop gain of

the error amplifier is limited by the open loop gain characteristic.

Therefore, the noise contribution from 20 kHz to 100 kHz is

less than what it is if the error amplifier had infinite bandwidth.

This is also the reason why the noise is less than what might be

expected simply based on the dc gain, that is, 70 µV rms vs.

110 µV rms.

FREQUENCY (Hz)

10M

1M

100k

10k

1k

100

10

1

1

10

100

10k

100k

1k

12V NOISE REDUCTION

12V NO NOISE REDUCTION

6V NOISE REDUCTION

6V NO NOISE REDUCTION

Figure 51. 6 V and 12 V Output Voltage with and Without Noise Reduction

Network

EFFECT OF NOISE REDUCTION ON START-UP TIME

The start-up time of the ADP7118 is affected by the noise

reduction network and must be considered in applications

where power supply sequencing is critical.

The noise reduction circuit adds a pole in the feedback loop,

slowing down the start-up time. To approximate the start-up time

for an adjustable model with a noise reduction network using the

following equation:

as shown in Figure 50, the start-up time is approximately 0.6 sec.

length of the start-up time instead of the soft start capacitor.