VSC8221 datasheet(39/138 Pages) MICROSEMI

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VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

39 of 40

Data is transferred over the iEEE SMi using 32-bit frames with an optional and arbitrary length preamble. The iEEE SMi frame

format is described in the following table.

• idle: During idle, the MDiO node goes to a high-impedance state. This allows an external pull-up resistor to pull the MDiO

node up to a logical “1” state. Since idle mode should not contain any transitions on MDiO, the number of bits is

undefined during idle.

• Preamble: For the VSC8221, the preamble is optional. By default, preambles are not expected or required. The preamble

is a string of “1”s. if it exists, the preamble must be at least one bit, but otherwise may be arbitrarily long. See Mii Register

1.6 for more information.

• Start of Frame: A “01” pattern indicates the start of frame. if these bits are anything other than “01”, all following bits are

ignored until the next “preamble:0” pattern is detected.

• Operation Code: A “10” pattern indicates a read. A “01” pattern indicates a write. if these bits are anything other than “01”

or “10”, all following bits are ignored until the next “preamble:0” pattern is detected.

• PHY Address: The next five bits are the PHY address. The PHY responds to a message frame only when the received

PHY address matches its physical address. The PHY's address is indicated by the CMODE1[2] and CMODE0[3:0] bits.

• Register Address: The next five bits are the register address.

• Turn-Around: The next two bits are “turn-around” (TA) bits. They are used to avoid contention when a read operation is

performed on the MDiO. During read operations, the VSC8221 will drive the second TA bit, which is a logical “0”.

• Data: The next sixteen bits are data bits. When data is being read from the PHY, data is valid at the output of the PHY

from one rising edge of MDC to the next rising edge of MDC. When data is being written to the PHY, data must be valid

around the rising edge of MDC.

• idle: The sequence is repeated.

The following two figures diagram iEEE SMi read and iEEE SMi write operations.

Figure 12. MDiO Read Frame

Table 19. SMi Frame Format

Direction

from

VSC8221

Preamble

Start of

Frame

Op Code

PHY

Address

Turn-

Around

Data

idle

# of

bits

2255216

Read

Output

Z’s

data

Z’s

input

1’s

addr

Z’s

Write

Output

Z’s

ZZZZZ’s

Z’s

ZZZ’s

Z’s

input

1’s

addr

data

Z’s

MDC

MDIO

Preamble

(optional)

SFD

Z10

Read

PHY Address

A4 A3 A2 A1 A0 R4 R3 R2 R1 R0

to PHY

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Idle

Station Manager Drives MDIO

PHY Drives MDIO

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