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VSC8221 数据表(PDF) 91 Page - Microsemi Corporation |
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VSC8221 数据表(HTML) 91 Page - Microsemi Corporation |
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91 / 138 page  VSC8221 Data Sheet VMDS-10106 Revision 4.1 December 2006 91 of 106 106 26.15 – interrupt Status When bit 26.15 is set to “1”, an unacknowledged interrupt is pending. The cause of the interrupt can be determined by reading the interrupt status bits in this register. This bit is automatically cleared when read. 26.14 – Reserved 26.13 – Link State-Change interrupt Status When the link status of the PHY changes, bit 26.13 is set to “1” if bit 25.13 is also set to “1”. This bit is automatically cleared when read. 26.12 – Reserved 26.11 – Auto-Negotiation Error interrupt Status When an error is detected by the Auto-Negotiation state machine, bit 26.11 is set to “1” if bit 25.11 is also set to “1”. This bit is automatically cleared when read. 26.10 – Auto-Negotiation-Done / interlock Done interrupt Status When the auto-negotiation state machine finishes a negotiation process, bit 26.10 is set to “1” if bit 25.10 is also set to “1”. This bit is automatically cleared when read. 26.9 – inline Powered Device Detected interrupt Status When a device requiring inline power over CAT-5 is detected, bit 26.9 is set to “1” if bit 25.9 is also set to “1”. This bit is automatically cleared when read. 26.8 – Symbol Error interrupt Status When a symbol error is detected by the descrambler, bit 26.8 is set to “1” if bit 25.8 is also set to “1”. This bit is automatically cleared when read. 26.7 – Descrambler Lock-Lost interrupt Status When the descrambler loses lock, bit 26.7 is set to “1” if bit 25.7 is also set to “1”. This bit is automatically cleared when read. 26.6 – TX FiFO interrupt Status When the TX FiFO enters an underflow or overflow condition, bit 26.6 is set to “1” if bit 25.6 is also set to “1”. This bit is automatically cleared when read. 26.5 – RX FiFO interrupt Status When the RX FiFO enters an underflow or overflow condition, bit 26.5 is set to “1” if bit 25.5 is also set to “1”. This bit is automatically cleared when read. 26.4 – Reserved 26.3 – False Carrier interrupt Status When the PHY has detected a false carrier, bit 26.3 is set to “1” if bit 25.3 is also set to “1”. This bit is automatically cleared when read, 26.2 – Cable impairment Detect interrupt Status When the PHY has detected an impairment on the CAT-5 media, bit 26.3 is set to “1” if bit 25.3 is also set to “1”. This bit is automatically cleared when read. |
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