ADA4355ABCZ datasheet(40/45 Pages) AD

40 / 45 page

ADA4355

Data Sheet

Rev. A | Page 40 of 45

Reg.

(Hex)

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Value

(Hex)

Comments

0x0D

Test mode (local

except for PN

sequence

resets)

User input test mode:

00 = single,

01 = alternate,

10 = single once,

11 = alternate once (affects

user input test mode only,

Bits[3:0] = 1000)

Reset

PN long

gen

Reset PN

short

gen

Output test mode, Bits[3:0] (local):

0000 = off (default),

0001 = midscale short,

0010 = positive full-scale,

0011 = negative full-scale,

0100 = alternating checkerboard,

0101 = PN23 sequence,

0110 = PN9 sequence,

0111 = one-/zero-word toggle,

1000 = user input,

1001 = 1-/0-bit toggle,

1010 = 1× sync,

1011 = one bit high,

1100 = mixed bit frequency

0x00

When set, the

test data is

placed on the

output balls

in place of

normal data.

0x14

Output mode

Open

LVDS-ANSI/

LVDS-IEEE

option:

0 = LVDS-ANSI,

1 = LVDS-IEEE

reduced range

link (global),

see Table 18

Open

Output

invert

(local)

Open

Output

format:

0 = offset

binary,

1 = twos

comple-

ment

(global)

0x01

Configures

the outputs

and format of

the data.

0x15

Output adjust

Open

Output driver

termination,

Bits[1:0]:

00 = none,

01 = 200 Ω,

10 = 100 Ω,

11 = 100 Ω

Open

Output

drive:

0 = 1×

drive,

1 = 2×

drive

0x00

Determines

LVDS or other

output

properties.

0x16

Output phase

Open

Input clock phase adjust, Bits[6:4]

(value is the number of input clock

cycles of phase delay), see Table 19

Output clock phase adjust, Bits[3:0]

(0000 through 1011), see Table 20

0x03

On devices

using global

clock divide,

determines

which phase

of the divider

output is used

to supply the

output clock.

Internal

latching is

unaffected.

0x19

USER_PATT1_

LSB (global)

0x00

User Defined

Pattern 1 LSB.

0x1A

USER_PATT1_

MSB (global)

B15

B14

B13

B12

B11

B10

0x00

User Defined

Pattern 1

MSB.

0x1B

USER_PATT2_

LSB (global)

0x00

User Defined

Pattern 2 LSB.

0x1C

USER_PATT2_

MSB (global)

B15

B14

B13

B12

B11

B10

0x00

User Defined

Pattern 2 MSB.

0x21

Serial output

data control

(global)

LVDS

output:

0 = MSB

first

(default),

1 = LSB first

SDR/DDR one-lane/two-lane,

bitwise/bytewise, Bits[6:4]:

000 = SDR two-lane, bitwise,

001 = SDR two-lane, bytewise,

010 = DDR two-lane, bitwise,

011 = DDR two-lane, bytewise (default) ,

100 = DDR one-lane, wordwise

Encode

mode :

0 =

normal

encode

rate mode

(default),

1 = low

encode

mode for

sample

rate of

<20 MSPS

0 = 1×

frame

(default),

1 = 2×

frame

Serial output

number of bits:

00 = 16 bits (default),

10 = 12 bits

0x30

Serial stream

control.

Sample rate of

<20 MSPS

requires that

Bits[6:4] = 100

(DDR one-lane)

and Bit 3 = 1

(low encode

mode).

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