ADA4355ABCZ datasheet(5/45 Pages) AD

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Data Sheet

ADA4355

Rev. A | Page 5 of 45

CLK, SPI, AND CONTROL SPECIFICATIONS

TA = 25°C, VCC = 3.3 V, and LDO enabled (see the power scheme shown in Figure 3), unless otherwise noted.

Table 3.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

CLOCK INPUTS (CLKP AND CLKN)

External Clock Frequency

1000

MHz

Conversion Rate

125

MSPS

Logic Compliance

CMOS/LVDS/LVPECL

Differential Input Voltage

For LVDS and LVPECL

0.2

3.6

V p-p

Input Voltage Range

GND − 0.2

VEA + 0.2

Input Common-Mode Voltage

0.9

Input Resistance (Differential)

kΩ

Input Capacitance, CIN

SERIAL PORT INTERFACE (SPI) CLOCK

SCLK Frequency

MHz

SPI INPUTS (SCLK, CS, AND SDIO)

Input High Voltage, VINH

1.2

VEA + 0.2

Input Low Voltage, VINL

0.8

SCLK

Input Resistance, RIN

kΩ

CIN

RIN

kΩ

CIN

SDIO

RIN

kΩ

CIN

SPI OUTPUT (SDIO)

Logic 1 Output Voltage

High output current (IOH) = 800 µA

1.79

Logic 0 Output Voltage

Low output current (IOL) = 50 µA

0.05

OTHER CONTROL INPUTS (GSEL0, GSEL1, FSEL,

AND VLDEN)

VINH

VCC

VINL

0.4

Input Low or High Current, IINL or IINH

Input voltage (VIN) = VINL or VINH

CIN

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