Data Sheet

ADA4355

Rev. A | Page 7 of 45

ADC LVDS OUTPUT SPECIFICATIONS

Table 5.

Temperature Min

Typ

Max

Unit

Input Rate

Full

10

1000

MHz

Full

10

125

MSPS

Pulse Width

Full

6.25 to 4.00

ns

Full

6.25 to 4.00

ns

Full

1.5

2.3

3.1

ns

Full

300

ps

Full

300

ps

Frame Clock Output (FCO) Propagation Delay,

Full

1.5

2.3

3.1

ns

Full

ns

Full

ps

Full

ps

Full

90

ps

Full

±50

±200

ps

Wake-Up Time (Standby)

25°C

250

ns

Wake-Up Time (Power-Down)

25°C

375

µs

Pipeline Latency

Full

16

Clock cycles

APERTURE

25°C

1

ns

25°C

174

fs rms

Out-of-Range Recovery Time

25°C

1

Clock cycles

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

These parameters were measured on standard FR4 materials.

3

The clock can be adjusted via the SPI.

4

The conversion rate is the clock rate after the divider. Valid for 2-lane operation.

5

This parameter is not shown in Figure 6 through Figure 11.

6