LTC7802EUFDM datasheet(26/34 Pages) AD

26 / 34 page

LTC7802

Rev. 0

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from the step change in output current may not be within

the bandwidth of the feedback loop, so this signal can-

not be used to determine phase margin. This is why it is

better to look at the ITH pin signal which is in the feed-

back loop and is the filtered and compensated control

loop response. The gain of the loop will be increased

by increasing RC and the bandwidth of the loop will be

increased by decreasing CC. If RC is increased by the same

factor that CC is decreased, the zero frequency will be kept

the same, thereby keeping the phase shift the same in the

most critical frequency range of the feedback loop. The

output voltage settling behavior is related to the stability

of the closed-loop system and will demonstrate the actual

overall supply performance.

A second, more severe transient is caused by switching

in loads with large (>1μF) supply bypass capacitors. The

discharged bypass capacitors are effectively put in parallel

with COUT, causing a rapid drop in VOUT. No regulator can

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

CLOAD to COUT is greater than 1:50, the switch rise time

should be controlled so that the load rise time is limited

to approximately CLOAD • 25μs/μF. Thus a 10μF capacitor

would require a 250μs rise time, limiting the charging

current to about 200mA.

Design Example

As a design example, assume VIN(NOMINAL) = 12V, VIN(MAX)

= 22V, VOUT = 3.3V, IOUT = 20A, and fSW = 1MHz.

1. Set the operating frequency. The frequency is not one

of the internal preset values, so a resistor from the

FREQ pin to GND is required, with a value of:

RFREQ(inkΩ)=

37MHz

1MHz

– 37k

2. Determine the inductor value. Initially select a value

based on an inductor ripple current of 30%. The

inductor value can then be calculated from the follow-

ing equation:

VOUT

fSW ΔIL

( )

1–

VOUT

VIN(NOM)

⎛

⎝

⎜

⎞

⎠

⎟ = 0.4µH

The highest value of ripple current occurs at the maxi-

mum input voltage. In this case the ripple at VIN = 22V

is 35%

3. Verify that the minimum on-time of 40ns is not vio-

lated. The minimum on-time occurs at VIN(MAX):

tON(MIN) =

VOUT

VIN(MAX)(fSW)

= 150ns

This is more than sufficient to satisfy the minimum on

time requirement. If the minimum on time is violated,

the LTC7802 skips pulses at high input voltage, result-

ing in lower frequency operation and higher inductor

current ripple than desired. If undesirable, this behav-

ior can be avoided by decreasing the frequency (with

the inductor value accordingly adjusted) to avoid oper-

ation near the minimum on-time.

4. Select the RSENSE resistor value. The peak inductor

current is the maximum DC output current plus half of

the inductor ripple current. Or 20A • (1+0.30/2) = 23A

in this case. The RSENSE resistor value can then be cal-

culated based on the minimum value for the maximum

current sense threshold (45mV):

RSENSE ≤

45mV

23A

≅ 2mΩ

To allow for additional margin, a lower value RSENSE

may be used (for example, 1.8mΩ); however, be sure

that the inductor saturation current has sufficient mar-

gin above VSENSE(MAX)/RSENSE, where the maximum

value of 55mV is used for VSENSE(MAX).

For this low inductor value and high current applica-

tion, an RC filter into the sense pins should be used

to compensate for the parasitic inductance (ESL) of

the sense resistor. Assuming an RSENSE geometry

of 1225 with a parasitic inductance of 0.2nH, the RC

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