LTC7802EUFDM datasheet(25/34 Pages) AD

25 / 34 page

LTC7802

Rev. 0

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3. I2R losses are predicted from the DC resistances of the

input fuse (if used), MOSFET, inductor, current sense

resistor, and input and output capacitor ESR. In contin-

uous mode the average output current flows through

L and RSENSE, but is chopped between the top and

bottom MOSFETs. If the two MOSFETs have approx-

imately the same RDS(ON), then the resistance of one

MOSFET can simply be summed with the resistances

of L, RSENSE and ESR to obtain I2R losses.

For example, if each RDS(ON) = 30mΩ, RL = 50mΩ,

RSENSE = 10mΩ and ESR = 40mΩ (sum of both input

and output capacitance losses), then the total resis-

tance is 130mΩ. This results in losses ranging from

3% to 13% as the output current increases from 1A to

5A for a 5V output, or a 4% to 20% loss for a 3.3V out-

put. This percentage loss varies as the inverse square

of VOUT for the same external components and output

power level. The combined effects of increasingly lower

output voltages and higher currents required by high

performance digital systems is not doubling but qua-

drupling the importance of loss terms in the switching

regulator system!

4. Transition losses apply only to the top MOSFETs and

become significant only when operating at higher

input voltages (typically 15V or greater). Transition

losses can be estimated from the equation for the

main switch power dissipation in the Power MOSFET

Selection section.

Other hidden losses such as copper trace and internal

battery resistances can account for an additional 5% to

10% efficiency degradation in portable systems. It is very

important to include these system level losses during the

design phase. The internal battery and fuse resistance

losses can be minimized by making sure that CIN has ade-

quate charge storage and very low ESR at the switching

frequency. A 25W supply will typically require a minimum

of 20μF to 40μF of capacitance having a maximum of

20mΩ to 50mΩ of ESR. The LTC7802 2-phase architec-

ture typically halves this input capacitance requirement

over competing solutions. Other losses including induc-

tor core losses generally account for less than 2% total

additional loss.

Checking Transient Response

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, VOUT shifts by an

amount equal to ΔILOAD • (ESR), where ESR is the effective

series resistance of COUT. ΔILOAD also begins to charge or

discharge COUT generating the feedback error signal that

forces the regulator to adapt to the current change and

return VOUT to its steady-state value. During this recovery

time VOUT can be monitored for excessive overshoot or

ringing, which would indicate a stability problem.

OPTI-LOOP compensation allows the transient response

to be optimized over a wide range of output capaci-

tance and ESR values. The availability of the ITH pin not

only allows optimization of control loop behavior, but it

also provides a DC coupled and AC filtered closed loop

response test point. The DC step, rise time and settling

at this test point truly reflects the closed loop response.

Assuming a predominantly second order system, phase

margin and/or damping factor can be estimated using the

percentage of overshoot seen at this pin. The bandwidth

can also be estimated by examining the rise time at the

pin. The ITH external components shown in the Typical

Applications circuits provide an adequate starting point

for most applications.

The ITH series RC-CC filter sets the dominant pole-zero

loop compensation. The values can be modified slightly

(from 0.5 to 2 times their initial values) to optimize tran-

sient response once the final PC layout is done and the

particular output capacitor type and value have been

determined. The output capacitors need to be selected

because the various types and values determine the loop

gain and phase. An output current pulse of 20% to 80%

of full-load current having a rise time of 1μs to 10μs will

produce output voltage and ITH pin waveforms that will

give a sense of the overall loop stability without breaking

the feedback loop.

Placing a power MOSFET directly across the output

capacitor and driving the gate with an appropriate signal

generator is a practical way to produce a realistic load

step condition. The initial output voltage step resulting

APPLICATIONS INFORMATION

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