Data Sheet

ADPA9002

Rev. 0 | Page 17 of 19

THEORY OF OPERATION

The ADPA9002 is a GaAs, MMIC, pHEMT, cascode distributed

power amplifier. The cascode distributed architecture of the

ADPA9002 uses a fundamental cell consisting of a stack of two

field effect transistors (FETs) with the source of the upper FET

connected to the drain of the lower FET. The fundamental cell

is then duplicated several times with an RFIN transmission line

interconnecting the gates of the lower FETs and an RFOUT

transmission line interconnecting the drains of the upper FETs.

ACG2

RFOUT/

ACG1

ACG3

RFIN

Figure 61. Simplified Schematic of the Cascode Distributed Amplifier

Additional circuit design techniques are used around each cell

to optimize the overall bandwidth, output power, and noise

figure. The major benefit of this architecture is that a high

output level is maintained across a bandwidth far greater than a

single instance of the fundamental cell provides. A simplified

schematic of this architecture is shown in Figure 61.

For simplified biasing without the need for a negative voltage

allowing adjustment of the quiescent drain current above and

below the 385 mA nominal. As an example, Figure 52 shows that,

drain currents from 250 mA to 450 mA can be obtained.

The ADPA9002 has single-ended input and output ports whose

impedances are nominally equal to 50 Ω over the dc to 10 GHz

frequency range. Consequently, the ADPA9002 can be directly

inserted into a 50 Ω system with no required impedance

matching circuitry. Similarly, the input and output impedances

are sufficiently stable across variations in temperature and

supply voltage so that no impedance matching compensation is

bias, requiring an RF choke through which dc bias is applied.

Though the device operates down to dc, blocking capacitors are

recommended at the RF input and output ports to prevent

damages on the RF stages when loading the dc bias supplies. The

RF choke and blocking capacitor at the RF output together

constitute a bias tee. In practice, the external RF choke and dc

blocking capacitor selections limit the lowest frequency of

operation.

ACG1 through ACG3 are nodes at which ac terminations

(capacitors) to ground can be provided. The use of such

terminations serves to roll off the gain at frequencies below

200 MHz, allowing the flattest possible gain response to be

obtained over various frequencies.

It is critical to supply low inductance ground connections to the

GND pins and to the package base exposed pad to ensure stable

operation. To achieve optimal performance from the ADPA9002

and to prevent damage to the device, do not exceed the absolute

maximum ratings.