ADPA9002ACGZN-R7 datasheet(18/19 Pages) AD

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ADPA9002

Data Sheet

Rev. 0 | Page 18 of 19

APPLICATIONS INFORMATION

Capacitive bypassing is required for VDD and VGG1, as shown in

Figure 62. Both the RFIN and RFOUT/VDD pins are dc-coupled.

Use of an external dc blocking capacitor at RFIN is recommended.

Use of an external RF choke plus a dc blocking capacitor (for

example, a bias tee) at the RFOUT/VDD pin is required. For

wideband applications, ensure that the frequency responses of

the external biasing and blocking components are adequate for

use across the entire frequency range of the application.

The ADPA9002 operates in either self biased or externally

biased mode. Ground the VGG1 pin to operate the device in self

biased mode. For the externally biased configuration, adjust the

VGG1 pin within −2 V to +0.5 V to set the target drain.

The recommended bias sequence during power-up for self biased

operation is as follows:

1. Connect the VGG1 pin to ground and ground all GND pins.

2. Set VDD to 12 V.

3. Apply the RF signal to the RFIN pin.

The recommended bias sequence during power-down for self

biased operation is as follows:

1. Turn off the RFIN signal.

2. Set VDD to 0 V.

The recommended bias sequence during power-up for externally

biased operation is as follows:

1. Connect all GND pins to ground.

2. Set the VGG1 pin to −2 V.

3. Set VDD to 12 V.

4. Increase the VGG1 pin to achieve the IDQ.

5. Apply the RF signal to the RFIN pin.

The recommended bias sequence during power-down for

externally biased operation is as follows:

1. Turn off the RFIN signal.

2. Decrease the VGG1 pin to −2 V to achieve a typical IDQ of 0 mA.

3. Set VDD to 0 V.

4. Set the VGG1 pin to 0 V.

Take care to ensure adherence to the values shown in the

Absolute Maximum Ratings section.

Unless otherwise noted, all measurements and data shown were

taken using the typical application circuit (see Figure 62) and

biased per the conditions in this section. The bias conditions

described in this section are the operating points recommended

to optimize the overall device performance. Operation using

other bias conditions may result in performance that differs

from what is shown in the Typical Performance Characteristics

section. To obtain optimal performance while not damaging the

device, follow the recommended biasing sequences described in

this section.

TYPICAL APPLICATION CIRCUIT

In Figure 62, the drain voltage (VDD) must be applied through an

external broadband bias tee connected at the RFOUT/VDD pin and

connect an external dc block to the RFIN pin. Use optional

capacitors if the device is operated below 200 MHz.

RFIN

RFOUT

NOTE 1

NOTE 2

NOTE 1

NOTES

1. DRAIN VOLTAGE (VDD) MUST BE APPLIED THROUGH AN ETERNAL BIAS TEE CONNECTED

AT THE RFOUT/VDD PIN AND AN EXTERNAL DC BLOCK MUST BE CONNECTED AT THE RFIN PIN.

2. USE OPTIONAL CAPACITORS IF THE DEVICE IS OPERATED BELOW 200MHz.

1000pF

0.01µF

4.7µF

VDD

VGG1

NOTE 2

0.01µF

C10

4.7µF

1000pF

0.01µF

C11

4.7µF

Figure 62. Typical Application Circuit

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