AS4LC2M8S1 datasheet(9/28 Pages) ALSC

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AS4LC2M8S1

AS4LC1M16S1

7/5/00

ALLIANCE SEMICONDUCTOR

Notes

1IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open.

Other input signals are allowed to transition no more than once in any two-clock period and are otherwise at valid V IH or VIL levels.

Address transitions average one transition every two-clock period.

4The IDD current will decrease as the CAS-latency is reduced. This is due to the fact that the maximum cycle rate is slower as the CAS-l atency is reduced.

5tCK = 7 ns for –7, 8 ns for –8, and 10 ns for –10.

6If clock tr > 1 ns, (tr/2 – 0.5)ns should be added to the parameter.

7If clock (tr and tf) > 1 ns, [(tr + tf)/2 – 1] ns should be added to the parameter.

8VIH overshoot: VIH(max) = VDDQ + 2V for a pulse width ≤ 3 ns, and the pulse width cannot be greater than one third of the cycle rate. V IL undershoot:

VIL(min) = –2V for a pulse width ≤ 3 ns and the pulse width cannot be greater than one third of the cycle rate.

Required clocks are specified by JEDEC functionalisty and are not dependent on any timing parameter.

10 The clock frequency must remain constant during access or precharge states (READ, WRITE, including tWR and PRECHARGE commands). CKE may be

used to reduce the data rate.

11 Timing actually specified tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate.

12 Timing actually specified by tWR.

13 tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH

before going to HIGH-Z.

14 CLK must be toggled a minimum of two times during this period.

15 Enables on-chip refresh and address counters.

16 All voltages referenced to VSS.

17 The minimum specifications are used only to indicate the cycle time at which proper operation over the full temperature range (0

° C ≤ T

A ≤ 70° C) is

endured.

tMRD

Load mode register to

active/refresh command

2–

–

tCK

tOH

Output data hold time @

30 pF

–

2.5

–

–ns

–

2.5

–

–ns

–

2.5

–

–ns

tPED

CKE to CLOCK enable or

power-down exit mode

1–

–

tCK

tRAS

Active to precharge

command

120,000

tRC Active command period

–

tRCAR Auto refresh period

–

tRCD

Active to read or write

delay

–

tREF

Refresh period—2048

rows

–64

–

tROH

Data-out high Z from

precharge/burst stop

command

–

tCK

–

tCK

–

tCK

tRP

Precharge command

period

–

tRRD

Active Bank A to Active

Bank B command

–

Transition time

0.3

1.0

0.3

1.0

0.3

1.0

tWR WRITE recovery time

–2–

–

tCK

tXSR

Exit SELF REFRESH to

ACTIVE command

–

Sym

Parameter

CAS

latency

–7

–8

–10

Unit

Notes

Min

Max

Min

Max

Min

Max

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