Symbol

Parameter

M48T36Y

Unit

-70

Min

Max

Write Cycle Time

70

ns

Address Valid to Write Enable Low

0

ns

Address Valid to Chip Enable Low

0

ns

Write Enable Pulse Width

50

ns

Chip Enable Low to Chip Enable High

55

ns

Write Enable High to Address Transition

0

ns

Chip Enable High to Address Transition

0

ns

Input Valid to Write Enable High

30

ns

Input Valid to Chip Enable High

30

ns

Write Enable High to Input Transition

5

ns

Chip Enable High to Input Transition

5

ns

(1, 2)

Write Enable Low to Output Hi-Z

25

ns

Address Valid to Write Enable High

60

ns

Address Valid to Chip Enable High

60

ns

(1, 2)

Write Enable High to Output Transition

5

ns

2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

Table 9. Write Mode AC Characteristics

Byte 7FF8h is the clock control register. This byte

controls user access to the clock information and

also stores the clock calibration setting.

Byte 7FF7h contains the watchdog timer setting.

The watchdog timer detects an out-of-control mi-

croprocessor and provides a reset or interrupt to it.

Byte 7FF2h-7FF5h are reserved for clock alarm

programming. These bytes can be used to set the

alarm. This will generate an active low signal on the

IRQ/FT pin when the alarm bytes match the date,

hours, minutes and seconds of the clock.

The eight clock bytes are not the actual clock

counters themselves; they are memory locations

consisting of BiPORT

™ read/write memory cells.

The M48T36 includes a clock control circuit which

updates the clock bytes with current information

once per second.

The information can be ac-

cessed by the user in the same manner as any

other location in the static memory array.

The M48T36 also has its own Power-fail Detect

circuit. The control circuitry constantly monitors the

single 5V supply for an out of tolerance condition.

protects the SRAM, providing a high degree of data

security in the midst of unpredictablesystem opera-

approximately 3V, the control circuitry connects the

battery which maintains data and clock operation

until valid power returns.

READ MODE

The M48T36 is in the Read Mode whenever W

(Write Enable) is high and E (Chip Enable) is low.

The unique address specified by the 15 Address

Inputs defines which one of the 32,768 bytes of

data is to be accessed. Valid data will be available

Time) after the last address input signal is stable,

providing that the E and G access times are also

satisfied. If the E and G access times are not met,

DESCRIPTION (cont’d)

7/17

M48T36