valid data will be available after the latter of the Chip

The state of the eight three-state Data I/O signals

is controlled by E and G. If the outputs are activated

are changed while E and G remain active, output

Time) but will go indeterminate until the next Ad-

dress Access.

WRITE MODE

The M48T36 is in the Write Mode whenever W and

E are low. The start of a write is referenced from the

latter occurring falling edge of W or E. A write is

terminated by the earlier rising edge of W or E. The

addresses must be held valid throughoutthe cycle.

initiation of another read or write cycle. Data-in

high during write cycles to avoid bus contention;

although, if the output bus has been activated by a

low on E and G a low on W will disable the outputs

DATA RETENTION MODE

conventional BYTEWIDE static RAM. Should the

supply voltage decay, the RAM will automatically

outputs become high impedance, and all inputs are

treated as ”don’t care.”

Note: A power failure during a write cycle may

corrupt data at the currently addressed location, but

does not jeopardize the rest of the RAM’s content.

sured the memory will be in a write protected state,

M48T36 may respond to transient noise spikes on

pling of the power supply lines is recommended.

switches power to the internal battery which pre-

serves data and powers the clock. The internal

button cell will maintain data in the M48T36 for an

POWER-ON RESET

pulls low (open drain) and remains low on power-up

Ω

resistor is recommended in order to control the rise

PROGRAMMABLE INTERRUPTS

The M48T36 has two programmable interrupts: an

alarm and a watchdog. When an interrupt condition

occurs, the M48T36 sets the appropriate flag bit in

the flag register 7FF0h. The interrupt enable bits in

7FF6h and the WDS (Watchdog Steering) bit in

7FF7h allow the interrupt to activate the IRQ/FT pin.

The interrupt flags and the IRQ/FT output are

cleared by a read to the flags register. An interrupt

condition reset will not occur unless the addresses

are stable at the flag location for at least 15ns while

the device is in the read mode as shown in Figure

10.

The IRQ/FT pin is an open drain output and re-

quires a pull-up resistor. The pin remains in the high

impedance state unless an interrupt occurs or the

frequency test mode is enabled.

CLOCK OPERATIONS

Reading the Clock

Updates to the TIMEKEEPER registers should be

halted before clock data is read to prevent reading

data in transition. Because the BiPORT TIME-

KEEPER cells in the RAM array are only data

registers, and not the actual clock counters, updat-

ing the registers can be halted without disturbing

the clock itself.

READ MODE (cont’d)

9/17

M48T36