AI01389B

VCC

IRQ/FT

HIGH-Z

VPFD (max)

VPFD (min)

AFE

AF

HIGH-Z

Figure 11. Back-up Mode Alarm Waveforms

WATCHDOG TIMER

The watchdog timer can be used to detect an

out-of-control microprocessor. The user programs

the watchdog timer by setting the desired amount

of time-out into the eight bit Watchdog Register,

address 7FF7h. The five bits (BMB4-BMB0) store

a binary multiplier and the two lower order bits

(RB1-RB0) select the resolution, where 00=1/16

second, 01=1/4 second, 10=1 second, and 11=4

seconds. The amount of time-out is then deter-

mined to be the multiplication of the five bit multi-

plier value with the resolution.

(For example:

writing 00001110 in the Watchdog Register = 3 x 1

or 3 seconds). If the processor does not reset the

timer within the specified period, the M48T36 sets

the WDF (Watchdog Flag) and generates a watch-

dog interrupt or a microprocessor reset.

The most significant bit of the Watchdog Register

is the Watchdog Steering Bit. When set to a ’0’, the

watchdog will activate the IRQ/FT pin when timed-

out. When WDS is set to a ’1’, the watchdog will

output a negative pulse on the RST pin for a dura-

tion of 40ms to 200ms. The Watchdog register and

the FT bit will reset to a ’0’ at the end of a watchdog

time-out when the WDS bit is set to a ’1’.

The watchdog timer resets when the microproces-

sor performs a read of the Watchdog Register. The

time-out period then starts over. The watchdog

timer is disabled by writing a value of 00000000 to

the eight bits in the Watchdog Register. The watch-

dog function is automatically disabled upon power-

up and the Watchdog Register is cleared. If the

watchdog function is set to output to the IRQ/FT pin

and the frequency test function is activated, the

watchdog function prevails and the frequency test

function is denied. The WDI pin contains a pull-up

resistor which is greater than 100k

Ω, and therefore

can be left unconnected if not used.

BATTERY LOW WARNING

The M48T36 checks it’s battery voltage on power-

up. The BL (Battery Low) bit D4 of 7FF0h will be

set on power-up if the battery voltage is less than

2.5V (typical).

POWER-ON DEFAULTS

Upon application of power to the device, the follow-

ing register bits are set to a ’0’ state: WDS = 0;

BMB0-BMB4 = 0; RB0-RB1 = 0; AFE = 0; ABE = 0.

13/17

M48T36